[GHC] #3019: sparc membar asm instruction requires mode parameter

[GHC]

#3019: sparc membar asm instruction requires mode parameter
----------------------------------+-----------------------------------------
    Reporter:  duncan             |        Owner:  simonmar
        Type:  bug                |       Status:  new     
    Priority:  normal             |    Milestone:          
   Component:  Compiler           |      Version:  6.11    
    Severity:  normal             |   Resolution:          
    Keywords:                     |   Difficulty:  Unknown 
    Testcase:  rts/testwsdeque.c  |           Os:  Solaris 
Architecture:  sparc              |  
----------------------------------+-----------------------------------------
Comment (by duncan):

 If we modify the `rts/parallel/WSDqueue.c` to omit the call to
 `store_load_barrier()` then running `testwsdeque` (with 3 threads) fails
 like so:

 {{{
 internal error: internal error: FAIL: 3461204 1 10FAIL: 3460860 2 10

     (GHC version 6.11.20090211 for sparc_sun_solaris2)
     Please report this as a GHC bug:
 http://www.haskell.org/ghc/reportabug
     (GHC version 6.11.20090211 for sparc_sun_solaris2)
     Please report this as a GHC bug:
 http://www.haskell.org/ghc/reportabug
 Abort (core dumped)
 }}}

 Clearly several threads are hitting internal errors and the messages are
 getting interleaved in the console output. With just two threads the
 output is more readable:

 {{{
 internal error: FAIL: 3456932 1 10
     (GHC version 6.11.20090211 for sparc_sun_solaris2)
     Please report this as a GHC bug:
 http://www.haskell.org/ghc/reportabug
 Abort (core dumped)
 }}}

 Note that at least one thread does not die and the test runs on for a
 second or so until it aborts.

 So the conclusion would seem to be that the attached patch works and that
 the store/load memory barrier is necessary on Sparc.

 As for performance, it is apparently a bit quicker than on x86 which is
 interesting. For reference, running the `testwsdeque` test prog with a 10x
 bigger problem size (ie `SCRATCH_SIZE`) on the UltraSPARC T2:

  * 3  threads: 1.6s
  * 4  threads: 1.6s
  * 8  threads: 1.9s
  * 16 threads: 3.4s
  * 32 threads: 8.3s
  * 64 threads: 18.6-19.2s (more variability)

-- 
Ticket URL: <http://hackage.haskell.org/trac/ghc/ticket/3019#comment:3>
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