[GHC] #3019: sparc membar asm instruction requires mode parameter

[GHC]

#3019: sparc membar asm instruction requires mode parameter
----------------------------------+-----------------------------------------
    Reporter:  duncan             |        Owner:  simonmar
        Type:  bug                |       Status:  new     
    Priority:  normal             |    Milestone:          
   Component:  Compiler           |      Version:  6.11    
    Severity:  normal             |   Resolution:          
    Keywords:                     |   Difficulty:  Unknown 
    Testcase:  rts/testwsdeque.c  |           Os:  Solaris 
Architecture:  sparc              |  
----------------------------------+-----------------------------------------
Comment (by duncan):

 {{{
 hunk ./includes/SMP.h 200
  #elif powerpc_HOST_ARCH
      __asm__ __volatile__ ("msync" : : : "memory");
  #elif sparc_HOST_ARCH
 -    /* Sparc in TSO mode does not require write/write barriers. */
 -    __asm__ __volatile__ ("membar" : : : "memory");
 +    __asm__ __volatile__ ("membar #StoreLoad" : : : "memory");
  #elif !defined(WITHSMP)
      return;
  #else
 }}}

 With this fix (darcs patch attached) `rts/parallel/WSDeque.c` compiles
 fine and the test program `rts/testwsdeque.c` appears to work (and runs
 very quickly on the T2 cpu).

 Out of interest we would like to see if we omit the membar if that causes
 the test program to fail in practice.

-- 
Ticket URL: <http://hackage.haskell.org/trac/ghc/ticket/3019#comment:2>
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