ARM64 Task Force

[Luke Iannini]

I've pushed my WIP patches here:
https://github.com/lukexi/llvm/commit/dfe74bb48eb05ce7847fa262f6e563d20d0b1fc5
https://github.com/lukexi/ghc/commit/e99b7a41e64f3ddb9bb420c0d5583f0e302e321e
(they also require the latest libffi to be dropped in
ftp://sourceware.org/pub/libffi/libffi-3.0.13.tar.gz due to
https://ghc.haskell.org/trac/ghc/ticket/8664)

These can produce an ARM64 GHC but the produced binaries aren't fully
functional yet. They make it through hs_init() but crash rather opaquely
when I try to call a simple fib function through the FFI.

It looks like it's jumping somewhere strange; lldb tells me it's to
0x100e05110:  .long  0x00000000                ; unknown opcode
0x100e05114:  .long  0x00000000                ; unknown opcode
0x100e05118:  .long  0x00000000                ; unknown opcode
0x100e0511c:  .long  0x00000000                ; unknown opcode
0x100e05120:  .long  0x00000000                ; unknown opcode
0x100e05124:  .long  0x00000000                ; unknown opcode
0x100e05128:  .long  0x00000000                ; unknown opcode
0x100e0512c:  .long  0x00000000                ; unknown opcode

If I put a breakpoint on StgRun and step by instruction, I seem to make it
to about:
https://github.com/lukexi/ghc/blob/e99b7a41e64f3ddb9bb420c0d5583f0e302e321e/rts/StgCRun.c#L770
(give or take a line)
before something goes mysteriously wrong and I'm no longer able to interact
with the debugger.

So I guess I'll try taking out float register support and see if that gets
me anywhere.

If anyone has some ideas on how to debug this I'd love to hear them! I've
mostly assembled the patches by adapting the existing ARM support so it's
quite possibly I'm doing something boneheaded.

Cheers
Luke



On Sun, Aug 10, 2014 at 6:44 PM, Luke Iannini <lukexipd at gmail.com> wrote:

> I think I've solved this particular mystery -- the registers were never
> defined there because that integer-representation of them is only used by
> the NCG. In LLVM land they were only ever stringified by the REG() macro.
>
> Except now globalRegMaybe is being used in CmmSink.hs (as Simon and Ben
> were discussing), and globalRegMaybe needs an integer value for each
> register to put into its Maybe RealReg return value. Since CmmSink.hs only
> checks 'isJust', it doesn't actually matter what the integer value is.
>
> So I've just gone ahead and defined them sequentially for now which seems
> to get me past this.
>
> Thanks!
> Luke
>
>
> On Sat, Aug 9, 2014 at 4:22 AM, Karel Gardas <karel.gardas at centrum.cz>
> wrote:
>
>> On 08/ 9/14 05:27 AM, Luke Iannini wrote:
>>
>>> Hi Karel,
>>> Thanks!
>>>
>>> A question:
>>> https://git.haskell.org/ghc.git/commitdiff/
>>> 454b34cb3b67dec21f023339c4d53d734af7605d
>>> adds references to s16, s17, s18, s19, d10 and d11 but I don't see those
>>>
>>
>> Yes, that adds FPU support for ARM.
>>
>>
>>  where I though to expect them in
>>> https://github.com/ghc/ghc/blob/master/includes/CodeGen.Platform.hs
>>>
>>
>> Hmm, whole ARM reg set is missing in this file. IIRC Simon Marlow were
>> discussing this with Ben Gamari recently. I've not investigated if this is
>> needed or not since I don't know if this is used only in NCG or in
>> registerised build in general. If the former, ARM will not be there as
>> there is no ARM NCG yet, if the later, then ARM should be there as
>> ARM/LLVM/registerised build is a reality.
>>
>> Cheers,
>> Karel
>>
>
>
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