ARM64 Task Force

[Karel Gardas]

On 08/12/14 11:03 AM, Luke Iannini wrote:
> It looks like it's jumping somewhere strange; lldb tells me it's to
> 0x100e05110: .long 0x00000000 ; unknown opcode
> 0x100e05114: .long 0x00000000 ; unknown opcode
> 0x100e05118: .long 0x00000000 ; unknown opcode
> 0x100e0511c: .long 0x00000000 ; unknown opcode
> 0x100e05120: .long 0x00000000 ; unknown opcode
> 0x100e05124: .long 0x00000000 ; unknown opcode
> 0x100e05128: .long 0x00000000 ; unknown opcode
> 0x100e0512c: .long 0x00000000 ; unknown opcode
>
> If I put a breakpoint on StgRun and step by instruction, I seem to make
> it to about:
> https://github.com/lukexi/ghc/blob/e99b7a41e64f3ddb9bb420c0d5583f0e302e321e/rts/StgCRun.c#L770
> (give or take a line)

strange that it's in the middle of the stp isns block. Anyway, this 
looks like a cpu exception doesn't it? You will need to find out the reg 
which holds the "exception reason" value and then look on it in your 
debugger to find out what's going wrong there.

Karel