[Haskell-cafe] Reduceron: reduced to numbers.

[Serguey Zefirov]

2010/12/4 Henning Thielemann <schlepptop at henning-thielemann.de>:
> Serguey Zefirov schrieb:
>
>> Of course, Reduceron in ASIC will require some cache memory, some
>> controllers, etc. So it won't be that small, like 230K transistors.
>> But, mzke it 2.3M transistors and it still be 2 orders of magnitude
>> less than Core2 Duo... ;)
> Cool! Do you have plans how it can be used eventually? As expansion
> card? As main processor? How to compile Haskell to Reduceron code?

I don't know answers to most of your questions.

But colleague of mine said that reduceron could be programmed into
FPGA part of upcoming Atom E600 - the one with Altera FPGA nearby.