[GHC] #5506: LLVM AST : needs an LlvmType ctor to represent vectors so that LLVM can generate SIMD instructions

[GHC]

#5506: LLVM AST : needs an LlvmType ctor to represent vectors so that LLVM can
generate SIMD instructions
--------------------------+-------------------------------------------------
 Reporter:  erikd         |          Owner:  dterei          
     Type:  task          |         Status:  closed          
 Priority:  normal        |      Component:  Compiler (LLVM) 
  Version:  7.3           |     Resolution:  wontfix         
 Keywords:                |       Testcase:                  
Blockedby:                |             Os:  Unknown/Multiple
 Blocking:                |   Architecture:  Unknown/Multiple
  Failure:  None/Unknown  |  
--------------------------+-------------------------------------------------

Comment(by dterei):

 http://hackage.haskell.org/trac/ghc/wiki/SimdLlvm

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Ticket URL: <http://hackage.haskell.org/trac/ghc/ticket/5506#comment:14>
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