potential for GHC benchmarks w.r.t. optimisations being incorrect

Sven Panne svenpanne at gmail.com
Mon May 7 11:04:38 UTC 2018

2018-05-06 16:41 GMT+02:00 Andreas Klebinger <klebinger.andreas at gmx.at>:

> [...] If we only consider 16byte (DSB Buffer) and 32 Byte (Cache Lines)
> relevant this reduces the possibilities by a lot after all. [...]

Nitpick: Cache lines on basically all Intel/AMD processors contain 64
bytes, see e.g. http://www.agner.org/optimize/microarchitecture.pdf
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