[Git][ghc/ghc][wip/supersven/riscv-vectors] mkSpillInstr: Refactor assertion
Sven Tennie (@supersven)
gitlab at gitlab.haskell.org
Sun Feb 16 17:31:27 UTC 2025
Sven Tennie pushed to branch wip/supersven/riscv-vectors at Glasgow Haskell Compiler / GHC
Commits:
3f4b5292 by Sven Tennie at 2025-02-16T18:29:38+01:00
mkSpillInstr: Refactor assertion
- - - - -
1 changed file:
- compiler/GHC/CmmToAsm/RV64/Instr.hs
Changes:
=====================================
compiler/GHC/CmmToAsm/RV64/Instr.hs
=====================================
@@ -339,22 +339,23 @@ mkSpillInstr ::
Int ->
[Instr]
mkSpillInstr _config (RegWithFormat reg fmt) delta slot =
- case off - delta of
- imm | fitsIn12bitImm imm && not (isVecFormat fmt) -> [mkStrSpImm imm]
- imm ->
- [ movImmToTmp imm,
- addSpToTmp,
- mkStrTmp
- ]
+ assertFmtReg fmt reg
+ $ case off - delta of
+ imm | fitsIn12bitImm imm && not (isVecFormat fmt) -> [mkStrSpImm imm]
+ imm ->
+ [ movImmToTmp imm,
+ addSpToTmp,
+ mkStrTmp
+ ]
where
fmt'
- | isVecFormat fmt
- = fmt
- | otherwise
- = scalarMoveFormat fmt
+ | isVecFormat fmt =
+ fmt
+ | otherwise =
+ scalarMoveFormat fmt
mkStrSpImm imm =
ANN (text "Spill@" <> int (off - delta))
- $ assertFmtReg II64 reg (STR fmt' (OpReg II64 reg) (OpAddr (AddrRegImm spMachReg (ImmInt imm))))
+ $ (STR fmt' (OpReg fmt reg) (OpAddr (AddrRegImm spMachReg (ImmInt imm))))
movImmToTmp imm =
ANN (text "Spill: TMP <- " <> int imm)
$ MOV tmp (OpImm (ImmInt imm))
@@ -363,8 +364,7 @@ mkSpillInstr _config (RegWithFormat reg fmt) delta slot =
$ ADD tmp tmp sp
mkStrTmp =
ANN (text "Spill@" <> int (off - delta))
- $ assertFmtReg II64 reg (STR fmt' (OpReg II64 reg) (OpAddr (AddrReg tmpReg)))
-
+ $ (STR fmt' (OpReg fmt reg) (OpAddr (AddrReg tmpReg)))
off = spillSlotToOffset slot
-- | Generate instructions to load a register from a spill slot.
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/commit/3f4b529260f9429a8ff1c6fc6d3ca6a44d2d8b43
--
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/commit/3f4b529260f9429a8ff1c6fc6d3ca6a44d2d8b43
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