[Git][ghc/ghc][wip/supersven/riscv-vectors] 2 commits: Fix MO_V_Extract and MO_VF_Extract
Sven Tennie (@supersven)
gitlab at gitlab.haskell.org
Sun Feb 16 17:23:31 UTC 2025
Sven Tennie pushed to branch wip/supersven/riscv-vectors at Glasgow Haskell Compiler / GHC
Commits:
e14c41cd by Sven Tennie at 2025-02-16T18:05:48+01:00
Fix MO_V_Extract and MO_VF_Extract
- - - - -
2f956385 by Sven Tennie at 2025-02-16T18:06:35+01:00
Assert register format in more places
Also, fix it.
- - - - -
2 changed files:
- compiler/GHC/CmmToAsm/RV64/CodeGen.hs
- compiler/GHC/CmmToAsm/RV64/Instr.hs
Changes:
=====================================
compiler/GHC/CmmToAsm/RV64/CodeGen.hs
=====================================
@@ -426,15 +426,16 @@ getRegisterReg platform (CmmGlobal mid) =
-- General things for putting together code sequences
-- | Compute an expression into any register
-getSomeReg :: CmmExpr -> NatM (Reg, Format, InstrBlock)
+getSomeReg :: HasCallStack => CmmExpr -> NatM (Reg, Format, InstrBlock)
getSomeReg expr = do
r <- getRegister expr
- case r of
- Any rep code -> do
- newReg <- getNewRegNat rep
- return (newReg, rep, code newReg)
- Fixed rep reg code ->
- return (reg, rep, code)
+ res@(reg, fmt, _) <- case r of
+ Any rep code -> do
+ newReg <- getNewRegNat rep
+ pure (newReg, rep, code newReg)
+ Fixed rep reg code ->
+ pure (reg, rep, code)
+ pure $ assertFmtReg fmt reg res
-- | Compute an expression into any floating-point register
--
@@ -1202,6 +1203,25 @@ getRegister' config plat expr =
expr
(op (OpReg format dst) (OpReg format_x reg_x) (OpReg format_y reg_y))
+ vecExtract format = do
+ (reg_v, format_v, code_v) <- getSomeReg x
+ (reg_idx, format_idx, code_idx) <- getSomeReg y
+ tmp <- getNewRegNat format_v
+ pure $ Any format $ \dst ->
+ code_v
+ `appOL` code_idx
+ `snocOL`
+ -- Setup
+ annExpr
+ expr
+ -- Move selected element to index 0
+ -- vslidedown.vi v8, v9, 2
+ (VSLIDEDOWN (OpReg format_v tmp) (OpReg format_v reg_v) (OpReg format_idx reg_idx))
+ `snocOL`
+ -- Move to float register
+ -- vmv.x.s a0, v8
+ VMV (OpReg format dst) (OpReg format_v tmp)
+
case op of
-- Integer operations
-- Add/Sub should only be Integer Options.
@@ -1254,8 +1274,8 @@ getRegister' config plat expr =
MO_S_Shr w -> intOp True w (\d x y -> unitOL $ annExpr expr (SRA d x y))
-- Vector operations
- MO_VF_Extract length w -> vecOp (floatVecFormat length w) VSLIDEDOWN
- MO_V_Extract length w -> vecOp (intVecFormat length w) VSLIDEDOWN
+ MO_VF_Extract length w -> vecExtract ((scalarFormatFormat . floatScalarFormat) w)
+ MO_V_Extract length w -> vecExtract ((scalarFormatFormat . intScalarFormat) w)
MO_VF_Add length w -> vecOp (floatVecFormat length w) VADD
MO_VF_Sub length w -> vecOp (floatVecFormat length w) VSUB
=====================================
compiler/GHC/CmmToAsm/RV64/Instr.hs
=====================================
@@ -354,7 +354,7 @@ mkSpillInstr _config (RegWithFormat reg fmt) delta slot =
= scalarMoveFormat fmt
mkStrSpImm imm =
ANN (text "Spill@" <> int (off - delta))
- $ STR fmt' (OpReg fmt' reg) (OpAddr (AddrRegImm spMachReg (ImmInt imm)))
+ $ assertFmtReg II64 reg (STR fmt' (OpReg II64 reg) (OpAddr (AddrRegImm spMachReg (ImmInt imm))))
movImmToTmp imm =
ANN (text "Spill: TMP <- " <> int imm)
$ MOV tmp (OpImm (ImmInt imm))
@@ -363,7 +363,7 @@ mkSpillInstr _config (RegWithFormat reg fmt) delta slot =
$ ADD tmp tmp sp
mkStrTmp =
ANN (text "Spill@" <> int (off - delta))
- $ STR fmt' (OpReg fmt' reg) (OpAddr (AddrReg tmpReg))
+ $ assertFmtReg II64 reg (STR fmt' (OpReg II64 reg) (OpAddr (AddrReg tmpReg)))
off = spillSlotToOffset slot
@@ -953,17 +953,18 @@ isFloatOp :: Operand -> Bool
isFloatOp op = isFloatRegOp op || isFloatImmOp op
-- TODO: Hide OpReg (Operand) constructor and use this guard to ensure only sane fmt/reg combinations can be used
-assertFmtReg :: HasCallStack => Format -> Reg -> a -> a
-assertFmtReg fmt reg| fmtRegCombinationIsSane fmt reg = id
-assertFmtReg fmt reg = pprPanic
- "Format does not fit to register."
- (text "fmt" <> colon <+> ppr fmt <+> text "reg" <> colon <+> ppr reg)
+assertFmtReg :: (HasCallStack) => Format -> Reg -> a -> a
+assertFmtReg fmt reg | fmtRegCombinationIsSane fmt reg = id
+assertFmtReg fmt reg =
+ pprPanic
+ "Format does not fit to register."
+ (text "fmt" <> colon <+> ppr fmt <+> text "reg" <> colon <+> ppr reg)
fmtRegCombinationIsSane :: Format -> Reg -> Bool
-fmtRegCombinationIsSane fmt reg =
- (isFloatFormat fmt && isFloatReg reg) ||
- (isIntFormat fmt && isIntReg reg) ||
- (isVecFormat fmt && isVectorReg reg)
+fmtRegCombinationIsSane fmt reg =
+ (isFloatFormat fmt && isFloatReg reg)
+ || (isIntFormat fmt && isIntReg reg)
+ || (isVecFormat fmt && isVectorReg reg)
isVectorRegOp :: Operand -> Bool
isVectorRegOp (OpReg fmt reg) | isVectorReg reg = assertFmtReg fmt reg $ True
@@ -976,12 +977,12 @@ isFloatReg _ = False
isIntReg :: Reg -> Bool
isIntReg (RegReal (RealRegSingle i)) | isIntRegNo i = True
-isIntReg (RegVirtual (VirtualRegD _)) = True
+isIntReg (RegVirtual (VirtualRegI _)) = True
isIntReg _ = False
isVectorReg :: Reg -> Bool
isVectorReg (RegReal (RealRegSingle i)) | isVectorRegNo i = True
-isVectorReg (RegVirtual (VirtualRegD _)) = True
+isVectorReg (RegVirtual (VirtualRegV128 _)) = True
isVectorReg _ = False
allVectorRegOps :: [Operand] -> Bool
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/compare/c166771226e3d4be115b5aaaffe0af81d7b80d27...2f9563854b4512cde4acc6bd3f4113fa71429b9e
--
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/compare/c166771226e3d4be115b5aaaffe0af81d7b80d27...2f9563854b4512cde4acc6bd3f4113fa71429b9e
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