[Git][ghc/ghc][wip/supersven/riscv64-ncg] Implement XOR

[Sven Tennie (@supersven)]

Sven Tennie pushed to branch wip/supersven/riscv64-ncg at Glasgow Haskell Compiler / GHC


Commits:
b1489bbd by Sven Tennie at 2023-05-27T11:02:58+02:00
Implement XOR

Delete EOR which does not exist on RISCV64.

- - - - -


3 changed files:

- compiler/GHC/CmmToAsm/RV64/CodeGen.hs
- compiler/GHC/CmmToAsm/RV64/Instr.hs
- compiler/GHC/CmmToAsm/RV64/Ppr.hs


Changes:

=====================================
compiler/GHC/CmmToAsm/RV64/CodeGen.hs
=====================================
@@ -931,7 +931,7 @@ getRegister' config plat expr
         -- Bitwise operations
         MO_And   w -> bitOp w (\d x y -> unitOL $ AND d x y)
         MO_Or    w -> bitOp w (\d x y -> unitOL $ OR d x y)
-        MO_Xor   w -> bitOp w (\d x y -> unitOL $ EOR d x y)
+        MO_Xor   w -> bitOp w (\d x y -> unitOL $ XOR d x y)
         MO_Shl   w -> intOp False w (\d x y -> unitOL $ LSL d x y)
         MO_U_Shr w -> intOp False w (\d x y -> unitOL $ LSR d x y)
         MO_S_Shr w -> intOp True  w (\d x y -> unitOL $ ASR d x y)


=====================================
compiler/GHC/CmmToAsm/RV64/Instr.hs
=====================================
@@ -89,6 +89,7 @@ regUsageOfInstr platform instr = case instr of
   DIV dst src1 src2        -> usage (regOp src1 ++ regOp src2, regOp dst)
   REM dst src1 src2        -> usage (regOp src1 ++ regOp src2, regOp dst)
   SUB dst src1 src2        -> usage (regOp src1 ++ regOp src2, regOp dst)
+  -- TODO: It's named DIVU in RISCV64 -> rename
   UDIV dst src1 src2       -> usage (regOp src1 ++ regOp src2, regOp dst)
 
   -- 2. Bit Manipulation Instructions ------------------------------------------
@@ -101,8 +102,9 @@ regUsageOfInstr platform instr = case instr of
   ASR dst src1 src2        -> usage (regOp src1 ++ regOp src2, regOp dst)
   BIC dst src1 src2        -> usage (regOp src1 ++ regOp src2, regOp dst)
   BICS dst src1 src2       -> usage (regOp src1 ++ regOp src2, regOp dst)
+  -- TODO: Unused and does not exist in RISCV64
   EON dst src1 src2        -> usage (regOp src1 ++ regOp src2, regOp dst)
-  EOR dst src1 src2        -> usage (regOp src1 ++ regOp src2, regOp dst)
+  XOR dst src1 src2        -> usage (regOp src1 ++ regOp src2, regOp dst)
   LSL dst src1 src2        -> usage (regOp src1 ++ regOp src2, regOp dst)
   LSR dst src1 src2        -> usage (regOp src1 ++ regOp src2, regOp dst)
   MOV dst src              -> usage (regOp src, regOp dst)
@@ -239,7 +241,7 @@ patchRegsOfInstr instr env = case instr of
     BIC o1 o2 o3   -> BIC  (patchOp o1) (patchOp o2) (patchOp o3)
     BICS o1 o2 o3  -> BICS (patchOp o1) (patchOp o2) (patchOp o3)
     EON o1 o2 o3   -> EON  (patchOp o1) (patchOp o2) (patchOp o3)
-    EOR o1 o2 o3   -> EOR  (patchOp o1) (patchOp o2) (patchOp o3)
+    XOR o1 o2 o3   -> XOR  (patchOp o1) (patchOp o2) (patchOp o3)
     LSL o1 o2 o3   -> LSL  (patchOp o1) (patchOp o2) (patchOp o3)
     LSR o1 o2 o3   -> LSR  (patchOp o1) (patchOp o2) (patchOp o3)
     MOV o1 o2      -> MOV  (patchOp o1) (patchOp o2)
@@ -622,7 +624,7 @@ data Instr
     | BIC Operand Operand Operand -- rd = rn & ~op2
     | BICS Operand Operand Operand -- rd = rn & ~op2
     | EON Operand Operand Operand -- rd = rn ⊕ ~op2
-    | EOR Operand Operand Operand -- rd = rn ⊕ op2
+    | XOR Operand Operand Operand -- rd = rn ⊕ op2
     -- | LSL Operand Operand Operand -- rd = rn ≪ rm  or rd = rn ≪ #i, i is 6 bits
     -- | LSR Operand Operand Operand -- rd = rn ≫ rm  or rd = rn ≫ #i, i is 6 bits
     | MOV Operand Operand -- rd = rn  or  rd = #i
@@ -700,7 +702,7 @@ instrCon i =
       BIC{} -> "BIC"
       BICS{} -> "BICS"
       EON{} -> "EON"
-      EOR{} -> "EOR"
+      XOR{} -> "XOR"
       LSL{} -> "LSL"
       LSR{} -> "LSR"
       MOV{} -> "MOV"


=====================================
compiler/GHC/CmmToAsm/RV64/Ppr.hs
=====================================
@@ -500,7 +500,7 @@ pprInstr platform instr = case instr of
   BIC o1 o2 o3  -> op3 (text "\tbic") o1 o2 o3
   BICS o1 o2 o3 -> op3 (text "\tbics") o1 o2 o3
   EON o1 o2 o3  -> op3 (text "\teon") o1 o2 o3
-  EOR o1 o2 o3  -> op3 (text "\teor") o1 o2 o3
+  XOR o1 o2 o3  -> op3 (text "\txor") o1 o2 o3
   LSL o1 o2 o3  -> op3 (text "\tsll") o1 o2 o3
   LSR o1 o2 o3  -> op3 (text "\tsrl") o1 o2 o3
   MOV o1 o2



View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/commit/b1489bbd71b228e5296c98c6f365c44678790ccc

-- 
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/commit/b1489bbd71b228e5296c98c6f365c44678790ccc
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