[Git][ghc/ghc][wip/supersven/riscv64-ncg] Replace UXTB & UXTH, Fix UDIV
Sven Tennie (@supersven)
gitlab at gitlab.haskell.org
Sat May 27 08:30:35 UTC 2023
Sven Tennie pushed to branch wip/supersven/riscv64-ncg at Glasgow Haskell Compiler / GHC
Commits:
63358eb4 by Sven Tennie at 2023-05-27T10:29:00+02:00
Replace UXTB & UXTH, Fix UDIV
Replace UXTB and UXTB with truncateReg as these instructions do not
exist in RISCV64. UDIV is named DIVU in RISCV64.
- - - - -
3 changed files:
- compiler/GHC/CmmToAsm/RV64/CodeGen.hs
- compiler/GHC/CmmToAsm/RV64/Instr.hs
- compiler/GHC/CmmToAsm/RV64/Ppr.hs
Changes:
=====================================
compiler/GHC/CmmToAsm/RV64/CodeGen.hs
=====================================
@@ -709,14 +709,14 @@ getRegister' config plat expr
where w' = formatToWidth (cmmTypeFormat (cmmRegType plat reg))
r' = getRegisterReg plat reg
- CmmMachOp (MO_U_Quot w) [x, y] | w == W8 -> do
- (reg_x, _format_x, code_x) <- getSomeReg x
- (reg_y, _format_y, code_y) <- getSomeReg y
- return $ Any (intFormat w) (\dst -> code_x `appOL` code_y `snocOL` annExpr expr (UXTB (OpReg w reg_x) (OpReg w reg_x)) `snocOL` (UXTB (OpReg w reg_y) (OpReg w reg_y)) `snocOL` (UDIV (OpReg w dst) (OpReg w reg_x) (OpReg w reg_y)))
- CmmMachOp (MO_U_Quot w) [x, y] | w == W16 -> do
- (reg_x, _format_x, code_x) <- getSomeReg x
- (reg_y, _format_y, code_y) <- getSomeReg y
- return $ Any (intFormat w) (\dst -> code_x `appOL` code_y `snocOL` annExpr expr (UXTH (OpReg w reg_x) (OpReg w reg_x)) `snocOL` (UXTH (OpReg w reg_y) (OpReg w reg_y)) `snocOL` (UDIV (OpReg w dst) (OpReg w reg_x) (OpReg w reg_y)))
+ CmmMachOp (MO_U_Quot w) [x, y] | w == W8 || w == W16 -> do
+ (reg_x, format_x, code_x) <- getSomeReg x
+ (reg_y, format_y, code_y) <- getSomeReg y
+ return $ Any (intFormat w) (\dst -> code_x `appOL`
+ truncateReg (formatToWidth format_x) w reg_x `appOL`
+ code_y `appOL`
+ truncateReg (formatToWidth format_y) w reg_y `snocOL`
+ annExpr expr (UDIV (OpReg w dst) (OpReg w reg_x) (OpReg w reg_y)))
-- 2. Shifts. x << n, x >> n.
CmmMachOp (MO_Shl w) [x, (CmmLit (CmmInt n _))] | w == W32, 0 <= n, n < 32 -> do
@@ -745,18 +745,14 @@ getRegister' config plat expr
CmmMachOp (MO_U_Shr w) [x, (CmmLit (CmmInt n _))] | w == W8, 0 <= n, n < 8 -> do
(reg_x, _format_x, code_x) <- getSomeReg x
return $ Any (intFormat w) (\dst -> code_x `snocOL` annExpr expr (UBFX (OpReg w dst) (OpReg w reg_x) (OpImm (ImmInteger n)) (OpImm (ImmInteger (8-n)))))
- CmmMachOp (MO_U_Shr w) [x, y] | w == W8 -> do
- (reg_x, _format_x, code_x) <- getSomeReg x
+ CmmMachOp (MO_U_Shr w) [x, y] | w == W8 || w == W16 -> do
+ (reg_x, format_x, code_x) <- getSomeReg x
(reg_y, _format_y, code_y) <- getSomeReg y
- return $ Any (intFormat w) (\dst -> code_x `appOL` code_y `snocOL` annExpr expr (UXTB (OpReg w reg_x) (OpReg w reg_x)) `snocOL` (ASR (OpReg w dst) (OpReg w reg_x) (OpReg w reg_y)))
+ return $ Any (intFormat w) (\dst -> code_x `appOL` code_y `appOL` truncateReg (formatToWidth format_x) w reg_x `snocOL` annExpr expr (ASR (OpReg w dst) (OpReg w reg_x) (OpReg w reg_y)))
CmmMachOp (MO_U_Shr w) [x, (CmmLit (CmmInt n _))] | w == W16, 0 <= n, n < 16 -> do
(reg_x, _format_x, code_x) <- getSomeReg x
return $ Any (intFormat w) (\dst -> code_x `snocOL` annExpr expr (UBFX (OpReg w dst) (OpReg w reg_x) (OpImm (ImmInteger n)) (OpImm (ImmInteger (16-n)))))
- CmmMachOp (MO_U_Shr w) [x, y] | w == W16 -> do
- (reg_x, _format_x, code_x) <- getSomeReg x
- (reg_y, _format_y, code_y) <- getSomeReg y
- return $ Any (intFormat w) (\dst -> code_x `appOL` code_y `snocOL` annExpr expr (UXTH (OpReg w reg_x) (OpReg w reg_x)) `snocOL` (ASR (OpReg w dst) (OpReg w reg_x) (OpReg w reg_y)))
CmmMachOp (MO_U_Shr w) [x, (CmmLit (CmmInt n _))] | w == W32, 0 <= n, n < 32 -> do
(reg_x, _format_x, code_x) <- getSomeReg x
@@ -1171,14 +1167,18 @@ genCondJump bid expr = do
let ubcond w cmp = do
-- compute both sides.
- (reg_x, _format_x, code_x) <- getSomeReg x
- (reg_y, _format_y, code_y) <- getSomeReg y
+ (reg_x, format_x, code_x) <- getSomeReg x
+ (reg_y, format_y, code_y) <- getSomeReg y
let x' = OpReg w reg_x
y' = OpReg w reg_y
return $ case w of
- W8 -> code_x `appOL` code_y `appOL` toOL [ UXTB x' x', UXTB y' y', (annExpr expr (BCOND cmp x' y' (TBlock bid))) ]
- W16 -> code_x `appOL` code_y `appOL` toOL [ UXTH x' x', UXTH y' y', (annExpr expr (BCOND cmp x' y' (TBlock bid))) ]
- _ -> code_x `appOL` code_y `appOL` toOL [ (annExpr expr (BCOND cmp x' y' (TBlock bid))) ]
+ w | w == W8 || w == W16 -> code_x `appOL`
+ truncateReg (formatToWidth format_x) w reg_x `appOL`
+ code_y `appOL`
+ truncateReg (formatToWidth format_y) w reg_y `appOL`
+ code_y `snocOL`
+ annExpr expr (BCOND cmp x' y' (TBlock bid))
+ _ -> code_x `appOL` code_y `snocOL` annExpr expr (BCOND cmp x' y' (TBlock bid))
sbcond w cmp = do
-- compute both sides.
=====================================
compiler/GHC/CmmToAsm/RV64/Instr.hs
=====================================
@@ -95,8 +95,6 @@ regUsageOfInstr platform instr = case instr of
SBFM dst src _ _ -> usage (regOp src, regOp dst)
UBFM dst src _ _ -> usage (regOp src, regOp dst)
UBFX dst src _ _ -> usage (regOp src, regOp dst)
- UXTB dst src -> usage (regOp src, regOp dst)
- UXTH dst src -> usage (regOp src, regOp dst)
-- 3. Logical and Move Instructions ------------------------------------------
AND dst src1 src2 -> usage (regOp src1 ++ regOp src2, regOp dst)
OR dst src1 src2 -> usage (regOp src1 ++ regOp src2, regOp dst)
@@ -232,8 +230,6 @@ patchRegsOfInstr instr env = case instr of
SBFM o1 o2 o3 o4 -> SBFM (patchOp o1) (patchOp o2) (patchOp o3) (patchOp o4)
UBFM o1 o2 o3 o4 -> UBFM (patchOp o1) (patchOp o2) (patchOp o3) (patchOp o4)
UBFX o1 o2 o3 o4 -> UBFX (patchOp o1) (patchOp o2) (patchOp o3) (patchOp o4)
- UXTB o1 o2 -> UXTB (patchOp o1) (patchOp o2)
- UXTH o1 o2 -> UXTH (patchOp o1) (patchOp o2)
-- 3. Logical and Move Instructions ----------------------------------------
AND o1 o2 o3 -> AND (patchOp o1) (patchOp o2) (patchOp o3)
@@ -558,8 +554,6 @@ data Instr
| DELTA Int
-- 0. Pseudo Instructions --------------------------------------------------
- | UXTB Operand Operand
- | UXTH Operand Operand
-- | SXTW Operand Operand
-- | SXTX Operand Operand
| PUSH_STACK_FRAME
@@ -617,12 +611,7 @@ data Instr
-- 2. Bit Manipulation Instructions ----------------------------------------
| SBFM Operand Operand Operand Operand -- rd = rn[i,j]
- -- SXTB = SBFM <Wd>, <Wn>, #0, #7
- -- SXTH = SBFM <Wd>, <Wn>, #0, #15
- -- SXTW = SBFM <Wd>, <Wn>, #0, #31
| UBFM Operand Operand Operand Operand -- rd = rn[i,j]
- -- UXTB = UBFM <Wd>, <Wn>, #0, #7
- -- UXTH = UBFM <Wd>, <Wn>, #0, #15
-- Signed/Unsigned bitfield extract
| UBFX Operand Operand Operand Operand -- rd = rn[i,j]
@@ -688,8 +677,6 @@ instrCon i =
LDATA{} -> "LDATA"
NEWBLOCK{} -> "NEWBLOCK"
DELTA{} -> "DELTA"
- UXTB{} -> "UXTB"
- UXTH{} -> "UXTH"
PUSH_STACK_FRAME{} -> "PUSH_STACK_FRAME"
POP_STACK_FRAME{} -> "POP_STACK_FRAME"
ADD{} -> "ADD"
=====================================
compiler/GHC/CmmToAsm/RV64/Ppr.hs
=====================================
@@ -483,15 +483,13 @@ pprInstr platform instr = case instr of
| isFloatOp o1 && isFloatOp o2 && isFloatOp o3 -> op3 (text "\tfsub") o1 o2 o3
| isImmOp o3 -> op3 (text "\taddi") o1 o2 (negOp o3)
| otherwise -> op3 (text "\tsub") o1 o2 o3
- UDIV o1 o2 o3 -> op3 (text "\tudiv") o1 o2 o3
+ UDIV o1 o2 o3 -> op3 (text "\tdivu") o1 o2 o3
-- 2. Bit Manipulation Instructions ------------------------------------------
SBFM o1 o2 o3 o4 -> op4 (text "\tsbfm") o1 o2 o3 o4
UBFM o1 o2 o3 o4 -> op4 (text "\tubfm") o1 o2 o3 o4
-- signed and unsigned bitfield extract
UBFX o1 o2 o3 o4 -> op4 (text "\tubfx") o1 o2 o3 o4
- UXTB o1 o2 -> op2 (text "\tuxtb") o1 o2
- UXTH o1 o2 -> op2 (text "\tuxth") o1 o2
-- 3. Logical and Move Instructions ------------------------------------------
AND o1 o2 o3 -> op3 (text "\tand") o1 o2 o3
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/commit/63358eb49f1e6e4c14027cfe35ae7af26f369d8f
--
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/commit/63358eb49f1e6e4c14027cfe35ae7af26f369d8f
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