[Git][ghc/ghc][wip/marge_bot_batch_merge_job] 21 commits: docs: document permissibility of -XOverloadedLabels (#24249)
Marge Bot (@marge-bot)
gitlab at gitlab.haskell.org
Wed Dec 27 14:46:44 UTC 2023
Marge Bot pushed to branch wip/marge_bot_batch_merge_job at Glasgow Haskell Compiler / GHC
Commits:
c247b6be by Zubin Duggal at 2023-12-25T16:01:23-05:00
docs: document permissibility of -XOverloadedLabels (#24249)
Document the permissibility introduced by
https://github.com/ghc-proposals/ghc-proposals/blob/master/proposals/0170-unrestricted-overloadedlabels.rst
- - - - -
e5b7eb59 by Ömer Sinan Ağacan at 2023-12-25T16:02:03-05:00
Fix a code block syntax in user manual sec. 6.8.8.6
- - - - -
ab5212e3 by Ben Gamari at 2023-12-27T09:46:21-05:00
cmm: Introduce MO_RelaxedRead
In hand-written Cmm it can sometimes be necessary to atomically load
from memory deep within an expression (e.g. see the `CHECK_GC` macro).
This MachOp provides a convenient way to do so without breaking the
expression into multiple statements.
- - - - -
a588a3fc by Ben Gamari at 2023-12-27T09:46:21-05:00
codeGen: Use relaxed accesses in ticky bumping
- - - - -
f8c4792e by Ben Gamari at 2023-12-27T09:46:21-05:00
base: use atomic write when updating timer manager
- - - - -
370cabba by Ben Gamari at 2023-12-27T09:46:21-05:00
Use relaxed atomics to manipulate TSO status fields
- - - - -
ed0be1e8 by Ben Gamari at 2023-12-27T09:46:21-05:00
rts: Add necessary barriers when manipulating TSO owner
- - - - -
df12a4d2 by Ben Gamari at 2023-12-27T09:46:21-05:00
rts: Use `switch` to branch on why_blocked
This is a semantics-preserving refactoring.
- - - - -
c92e50b4 by Ben Gamari at 2023-12-27T09:46:21-05:00
rts: Fix synchronization on thread blocking state
We now use a release barrier whenever we update a thread's blocking
state. This required widening StgTSO.why_blocked as AArch64 does not
support atomic writes on 16-bit values.
- - - - -
c279e505 by Ben Gamari at 2023-12-27T09:46:21-05:00
rts: Fix data race in threadPaused
This only affects an assertion in the debug RTS and only needs relaxed
ordering.
- - - - -
44aca189 by Ben Gamari at 2023-12-27T09:46:21-05:00
rts: Fix data race in threadStatus#
- - - - -
1d76d386 by Ben Gamari at 2023-12-27T09:46:21-05:00
rts: Fix data race in Interpreter's preemption check
- - - - -
5974eda3 by Ben Gamari at 2023-12-27T09:46:21-05:00
rts/Messages: Fix data race
- - - - -
37b96848 by Ben Gamari at 2023-12-27T09:46:21-05:00
rts/Prof: Fix data race
- - - - -
142a80c2 by Ben Gamari at 2023-12-27T09:46:21-05:00
rts: Use relaxed ordering on dirty/clean info tables updates
When changing the dirty/clean state of a mutable object we needn't have
any particular ordering.
- - - - -
4dc6a137 by Ben Gamari at 2023-12-27T09:46:21-05:00
codeGen: Use relaxed-read in closureInfoPtr
- - - - -
2874af97 by Ben Gamari at 2023-12-27T09:46:21-05:00
STM: Use acquire loads when possible
Full sequential consistency is not needed here.
- - - - -
d339b5a9 by Ben Gamari at 2023-12-27T09:46:21-05:00
rts: Use fence rather than redundant load
Previously we would use an atomic load to ensure acquire ordering.
However, we now have `ACQUIRE_FENCE_ON`, which allows us to express this
more directly.
- - - - -
7d563f02 by Ben Gamari at 2023-12-27T09:46:21-05:00
rts: Fix data races in profiling timer
- - - - -
abe15a86 by Ben Gamari at 2023-12-27T09:46:21-05:00
Add Note [C11 memory model]
- - - - -
589d5cfc by Xiaoyan Ren at 2023-12-27T09:46:24-05:00
Do not color the diagnostic code in error messages (#24172)
- - - - -
30 changed files:
- compiler/GHC/Cmm/Expr.hs
- compiler/GHC/Cmm/Info.hs
- compiler/GHC/Cmm/MachOp.hs
- compiler/GHC/Cmm/Parser.y
- compiler/GHC/Cmm/ThreadSanitizer.hs
- compiler/GHC/CmmToAsm/AArch64/CodeGen.hs
- compiler/GHC/CmmToAsm/PPC/CodeGen.hs
- compiler/GHC/CmmToAsm/Wasm/FromCmm.hs
- compiler/GHC/CmmToAsm/X86/CodeGen.hs
- compiler/GHC/CmmToC.hs
- compiler/GHC/CmmToLlvm/CodeGen.hs
- compiler/GHC/StgToCmm/Ticky.hs
- compiler/GHC/StgToCmm/Utils.hs
- compiler/GHC/Types/Error.hs
- docs/users_guide/exts/instances.rst
- docs/users_guide/exts/overloaded_labels.rst
- libraries/base/src/GHC/Event/Thread.hs
- rts/Exception.cmm
- rts/HeapStackCheck.cmm
- rts/Interpreter.c
- rts/Messages.c
- rts/PrimOps.cmm
- rts/Proftimer.c
- rts/RaiseAsync.c
- rts/STM.c
- rts/Schedule.c
- rts/StgMiscClosures.cmm
- rts/StgStartup.cmm
- rts/ThreadPaused.c
- rts/Threads.c
The diff was not included because it is too large.
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/compare/85ca8a84190aa7427d6157d94c49409b91b11261...589d5cfc87f31657478d311d6dea1204ab41ec98
--
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/compare/85ca8a84190aa7427d6157d94c49409b91b11261...589d5cfc87f31657478d311d6dea1204ab41ec98
You're receiving this email because of your account on gitlab.haskell.org.
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://mail.haskell.org/pipermail/ghc-commits/attachments/20231227/42a91784/attachment-0001.html>
More information about the ghc-commits
mailing list