[commit: ghc] master: Add CMOVcc insns to x86 NCG (9f285fa)

[git at git.haskell.org]

Repository : ssh://git@git.haskell.org/ghc

On branch  : master
Link       : http://ghc.haskell.org/trac/ghc/changeset/9f285fa40f6fb0c8495dbec771d798ac6dfaabee/ghc

>---------------------------------------------------------------

commit 9f285fa40f6fb0c8495dbec771d798ac6dfaabee
Author: Herbert Valerio Riedel <hvr at gnu.org>
Date:   Mon Aug 11 12:38:09 2014 +0200

    Add CMOVcc insns to x86 NCG
    
    This is a pre-requisite for implementing count-{leading,trailing}-zero
    prim-ops (re #9340) and may be useful to NCG to help turn some code into
    branch-less code sequences.
    
    Test Plan: Compiles and validates in combination with clz/ctz primop impl
    
    Reviewers: ezyang, rwbarton, simonmar, austin
    
    Subscribers: simonmar, relrod, ezyang, carter
    
    Differential Revision: https://phabricator.haskell.org/D141


>---------------------------------------------------------------

9f285fa40f6fb0c8495dbec771d798ac6dfaabee
 compiler/nativeGen/X86/Instr.hs |  3 +++
 compiler/nativeGen/X86/Ppr.hs   | 15 +++++++++++++++
 2 files changed, 18 insertions(+)

diff --git a/compiler/nativeGen/X86/Instr.hs b/compiler/nativeGen/X86/Instr.hs
index 9c67266..ef0ceea 100644
--- a/compiler/nativeGen/X86/Instr.hs
+++ b/compiler/nativeGen/X86/Instr.hs
@@ -182,6 +182,7 @@ data Instr
 
         -- Moves.
         | MOV         Size Operand Operand
+        | CMOV   Cond Size Operand Reg
         | MOVZxL      Size Operand Operand -- size is the size of operand 1
         | MOVSxL      Size Operand Operand -- size is the size of operand 1
         -- x86_64 note: plain mov into a 32-bit register always zero-extends
@@ -356,6 +357,7 @@ x86_regUsageOfInstr :: Platform -> Instr -> RegUsage
 x86_regUsageOfInstr platform instr
  = case instr of
     MOV    _ src dst    -> usageRW src dst
+    CMOV _ _ src dst    -> mkRU (use_R src [dst]) [dst]
     MOVZxL _ src dst    -> usageRW src dst
     MOVSxL _ src dst    -> usageRW src dst
     LEA    _ src dst    -> usageRW src dst
@@ -532,6 +534,7 @@ x86_patchRegsOfInstr :: Instr -> (Reg -> Reg) -> Instr
 x86_patchRegsOfInstr instr env
  = case instr of
     MOV  sz src dst     -> patch2 (MOV  sz) src dst
+    CMOV cc sz src dst  -> CMOV cc sz (patchOp src) (env dst)
     MOVZxL sz src dst   -> patch2 (MOVZxL sz) src dst
     MOVSxL sz src dst   -> patch2 (MOVSxL sz) src dst
     LEA  sz src dst     -> patch2 (LEA  sz) src dst
diff --git a/compiler/nativeGen/X86/Ppr.hs b/compiler/nativeGen/X86/Ppr.hs
index 0aa7b9e..89bb0b0 100644
--- a/compiler/nativeGen/X86/Ppr.hs
+++ b/compiler/nativeGen/X86/Ppr.hs
@@ -521,6 +521,9 @@ pprInstr (RELOAD slot reg)
 pprInstr (MOV size src dst)
   = pprSizeOpOp (sLit "mov") size src dst
 
+pprInstr (CMOV cc size src dst)
+  = pprCondOpReg (sLit "cmov") size cc src dst
+
 pprInstr (MOVZxL II32 src dst) = pprSizeOpOp (sLit "mov") II32 src dst
         -- 32-to-64 bit zero extension on x86_64 is accomplished by a simple
         -- movl.  But we represent it as a MOVZxL instruction, because
@@ -1121,6 +1124,18 @@ pprSizeOpReg name size op1 reg2
         pprReg (archWordSize (target32Bit platform)) reg2
     ]
 
+pprCondOpReg :: LitString -> Size -> Cond -> Operand -> Reg -> SDoc
+pprCondOpReg name size cond op1 reg2
+  = hcat [
+        char '\t',
+        ptext name,
+        pprCond cond,
+        space,
+        pprOperand size op1,
+        comma,
+        pprReg size reg2
+    ]
+
 pprCondRegReg :: LitString -> Size -> Cond -> Reg -> Reg -> SDoc
 pprCondRegReg name size cond reg1 reg2
   = hcat [