[commit: ghc] master: Add bit scan {forward, reverse} insns to x86 NCG (3669b60)

[git at git.haskell.org]

Repository : ssh://git@git.haskell.org/ghc

On branch  : master
Link       : http://ghc.haskell.org/trac/ghc/changeset/3669b60cb0b24e22563bfe624aab4aba369cbfca/ghc

>---------------------------------------------------------------

commit 3669b60cb0b24e22563bfe624aab4aba369cbfca
Author: Herbert Valerio Riedel <hvr at gnu.org>
Date:   Mon Aug 11 09:54:36 2014 +0200

    Add bit scan {forward,reverse} insns to x86 NCG
    
    This is a pre-requisite for implementing count-{leading,trailing}-zero
    prim-ops (re #9340)
    
    Reviewers: ezyang, rwbarton, simonmar, austin
    
    Subscribers: simonmar, relrod, ezyang, carter
    
    Differential Revision: https://phabricator.haskell.org/D141


>---------------------------------------------------------------

3669b60cb0b24e22563bfe624aab4aba369cbfca
 compiler/nativeGen/X86/Instr.hs | 10 ++++++++--
 compiler/nativeGen/X86/Ppr.hs   |  2 ++
 2 files changed, 10 insertions(+), 2 deletions(-)

diff --git a/compiler/nativeGen/X86/Instr.hs b/compiler/nativeGen/X86/Instr.hs
index b8b81ae..9c67266 100644
--- a/compiler/nativeGen/X86/Instr.hs
+++ b/compiler/nativeGen/X86/Instr.hs
@@ -326,8 +326,10 @@ data Instr
                                  --       call 1f
                                  -- 1:    popl %reg
 
-    -- SSE4.2
-        | POPCNT      Size Operand Reg -- src, dst
+    -- bit counting instructions
+        | POPCNT      Size Operand Reg -- [SSE4.2] count number of bits set to 1
+        | BSF         Size Operand Reg -- bit scan forward
+        | BSR         Size Operand Reg -- bit scan reverse
 
     -- prefetch
         | PREFETCH  PrefetchVariant Size Operand -- prefetch Variant, addr size, address to prefetch
@@ -439,6 +441,8 @@ x86_regUsageOfInstr platform instr
     DELTA   _           -> noUsage
 
     POPCNT _ src dst -> mkRU (use_R src []) [dst]
+    BSF    _ src dst -> mkRU (use_R src []) [dst]
+    BSR    _ src dst -> mkRU (use_R src []) [dst]
 
     -- note: might be a better way to do this
     PREFETCH _  _ src -> mkRU (use_R src []) []
@@ -610,6 +614,8 @@ x86_patchRegsOfInstr instr env
     CLTD _              -> instr
 
     POPCNT sz src dst -> POPCNT sz (patchOp src) (env dst)
+    BSF    sz src dst -> BSF    sz (patchOp src) (env dst)
+    BSR    sz src dst -> BSR    sz (patchOp src) (env dst)
 
     PREFETCH lvl size src -> PREFETCH lvl size (patchOp src)
 
diff --git a/compiler/nativeGen/X86/Ppr.hs b/compiler/nativeGen/X86/Ppr.hs
index 6e2da18..0aa7b9e 100644
--- a/compiler/nativeGen/X86/Ppr.hs
+++ b/compiler/nativeGen/X86/Ppr.hs
@@ -581,6 +581,8 @@ pprInstr (XOR FF64 src dst) = pprOpOp (sLit "xorpd") FF64 src dst
 pprInstr (XOR size src dst) = pprSizeOpOp (sLit "xor")  size src dst
 
 pprInstr (POPCNT size src dst) = pprOpOp (sLit "popcnt") size src (OpReg dst)
+pprInstr (BSF size src dst)    = pprOpOp (sLit "bsf")    size src (OpReg dst)
+pprInstr (BSR size src dst)    = pprOpOp (sLit "bsr")    size src (OpReg dst)
 
 pprInstr (PREFETCH NTA size src ) =  pprSizeOp_ (sLit "prefetchnta") size src
 pprInstr (PREFETCH Lvl0 size src) = pprSizeOp_ (sLit "prefetcht0") size src