[Haskell] ANNOUNCE: The Reduceron

Matthew Naylor mfn-haskell at cs.york.ac.uk
Wed May 30 11:29:03 EDT 2007

Dear Haskellers,

You may be interested in the Reduceron:


Here is a flavour:

"The Reduceron is a processor for executing Haskell programs on FPGA
with the aim of exploring how custom architectural features can
improve the speed in which Haskell functions are evaluated. Being
described entirely in Haskell (using Lava), the Reduceron also serves
as an interesting application of functional languages to the design of
complex control circuits such as processors.

To program the Reduceron we provide a basic Haskell compiler, called
Tred, that translates Yhc.Core programs into codes of the Reduceron's
instruction set.

The Tred compiler and Reduceron processor are in the early stages of
development: they are both fairly naive, inefficient, and lacking in
many important features. But they represent a good start, already
capable of correctly compiling and executing (on FPGA) a reasonable
range of Haskell programs."

See webpage for more details.


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