[Haskell-cafe] CPU with Haskell support
dedgrant at gmail.com
Tue Jan 19 23:00:12 UTC 2016
Limiting the scope for my own sanity here, there may yet be some
application in various hardware level emulations of continuation passing
calculi, perhaps building on static single assignment.
It might be possoble to derive an interesting instruction set from the
sorts of intermediate representations we see in compiler infrastructures
like LLVM, but it is hard to guess how these hardware designs would benefit
haskell, rather than the other way around.
On Jan 19, 2016 14:44, "Auke Booij" <auke at tulcod.com> wrote:
> This question is much more involved than you seem to be suggesting.
> It's not just about adding "some instructions for Haskell support".
> You have to think about how you want to express /every/ haskell term
> as a series of bits (preferably predictably many bits), and find a
> (finite) combination of logical gates to do arbitrary computations
> with them.
> If you want to go anywhere in this directions, perhaps a good start
> would be implementing a processor with instructions for (untyped)
> lambda calculus. One approach for this could be to take a
> (mathematical) model of lambda calculus and see how its elements can
> be represented as natural numbers.
> This implementation, I suspect, would be terribly inefficient. Think
> about what the lambda application gate would look like in terms of
> NAND gates. Yes, it can probably be done in theory. No, it won't be
> pretty. And forget about practical.
> Finally, a major advantage of having such "raw" language as an
> instruction set is that it allows many many optimizations (e.g.
> pipelining (which, I would say, is the single most important reason
> that processors are able to run at GHzs instead of MHzs (Pentium 4
> processors, famed for their high clock speed, had 31 pipeline
> stages))) that I cannot imagine being possible in anything close to a
> "lambda calculus processor".
> What is the added value you hope to achieve?
> On 19 January 2016 at 22:12, Henning Thielemann
> <lemming at henning-thielemann.de> wrote:
> > Hi all,
> > every now and then I think it would be cool to have a microprocessor that
> > supports Haskell in a way. A processor where lazy evaluation is not
> > but an optimization opportunity, a processor that can make use of the
> > explicit data dependencies in Haskell programs in order to utilize many
> > computation units in parallel. I know of the Reduceron project, which
> > evolves only slowly and if it somewhen is ready for use it is uncertain
> > whether it can compete with stock CPUs since FPGA's need much more chip
> > space for the same logic.
> > I got to know that in todays x86 processors you can alter the instruction
> > set, which is mainly used for bugfixes. Wouldn't it be interesting to add
> > some instructions for Haskell support? However, I suspect that such a
> > might be rendered invalid by new processor generations with changed
> > details. Fortunately, there are processors that are designed for custom
> > instruction set extensions:
> > https://en.wikipedia.org/wiki/Xtensa
> > Would it be sensible to create a processor based on such a design? I
> have no
> > idea what it might cost, and you would still need some peripheral
> > to run it. What could processor instructions for Haskell support look
> > Has anyone already thought in this direction?
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