[Haskell-cafe] Reduceron: reduced to numbers.

Serguey Zefirov sergueyz at gmail.com
Sat Nov 27 20:02:02 CET 2010

I decided to calculate Reduceron's number of transistors (I had to, we
have some argument here;).

Reduceron allocate 14% of 17300 slices of Virtex-5 FPGA. If we assume
that each slice correspond to 8 4-input NAND-NOT elements, we will get
20000 4-input NAND. Each 4-input NAND contains 8 transistors, so the
count of logic transistors is about 160000.

Reduceron use 90% of 1.5Kbyte RAM blocks. Using 6 transistors per RAM
bit, we get 66K transistors more.

So Reduceron should contain about 230K transistors if someone decides
to go ASIC. It's 3 orders of magnitude less than x86, on par with most
late chips of Chuck Moore (inventor of Forth, MISC concept and the one
who develops some strange chips in GreenArrays
http://greenarraychips.com/ now).

The difference between Reduceron and GA144 of Chuck Moore is that
Reduceron could be programmed much more easily, and that rocks.

Clock frequency of 96MHz should go up too. My experience suggest
numbers between 5 and 8 times. So single Reduceron should be of equal
performance to Core2 Duo, at least.

Of course, Reduceron in ASIC will require some cache memory, some
controllers, etc. So it won't be that small, like 230K transistors.
But, mzke it 2.3M transistors and it still be 2 orders of magnitude
less than Core2 Duo... ;)

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