[Haskell-cafe] Ph.D. positions on HW acceleration of Haskell

[Rami Mukhtar]

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Vacancies for Ph.D. positions at NICTA with the University of Sydney, Australia
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Background
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NICTA has established a project with a goal of developing technology to map high level descriptions of computer vision algorithms to heterogeneous parallel hardware architectures. NICTA scholarships are available at the University of Sydney for outstanding students in the areas listed below. For further information, please contact either:
Dr Rami Mukhtar (rami.mukhtar _AT_ nicta.com.au) or
Dr Philip Leong (philip.leong _AT_ sydney.edu.au).

Further information concerning these scholarships is available from:
http://www.nicta.com.au/education/scholarships/sydney_research_lab/scholarship_opportunities_at_the_university_of_sydney


Reconfigurable Computing Architectures for Acceleration of Functional Languages
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This project would provide a candidate with the opportunity to develop new reconfigurable computing hardware architectures that are well suited for accelerating computations on collections of data.  The work would be driven by recent advances on computations of collections made in the functional language community.  The outcomes of this research would be to develop new hardware accelerator architectures, supporting tools chains, and undertake performance analysis.  The candidate would be part of a larger team working to develop a technology for mapping computer vision algorithms to heterogeneous parallel hardware architectures.

Hardware Acceleration of Functional Languages
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This project would provide a candidate with the opportunity to develop new methods for mapping functional languages to implementations that target hardware accelerators, including FPGAs and other reconfigurable computing architectures.  The outcomes of this research would be to develop algorithms, methodologies and related software frameworks that make this possible.  The candidate would be part of a larger team working to develop a technology for mapping computer vision algorithms to heterogeneous parallel hardware architectures.


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