[Haskell-cafe] What I learned from my first serious attempt low-level Haskell programming

[Stefan O'Rear]

On Thu, Apr 05, 2007 at 02:50:49PM +0400, Bulat Ziganshin wrote:
> Hello Stefan,
> 
> Thursday, April 5, 2007, 3:11:31 AM, you wrote:
> 
> > 2. Parameters are very expensive.
> 
> you should look at the asm code GHC generates. afair parameters are
> kept in stack and copied on each call (to the same place!). such sort
> of things are also very dependent on backend used - was it a ASM or C
> one?

Yes, I will update the wiki.

ghc -O2, where

stefan at stefans:~$ ghc -V
The Glorious Glasgow Haskell Compilation System, version 6.7.20070402
stefan at stefans:~$ uname -a
Linux stefans 2.6.18-3-686 #1 SMP Sun Dec 10 19:37:06 UTC 2006 i686 GNU/Linux
stefan at stefans:~$ cpuid
 eax in    eax      ebx      ecx      edx
00000000 00000002 756e6547 6c65746e 49656e69
00000001 00000f24 00010809 00000000 3febfbff
00000002 665b5001 00000000 00000000 007b7040
80000000 80000004 00000000 00000000 00000000
80000001 00000000 00000000 00000000 00000000
80000002 20202020 20202020 20202020 6e492020
80000003 286c6574 50202952 69746e65 52286d75
80000004 20342029 20555043 30302e32 007a4847

Vendor ID: "GenuineIntel"; CPUID level 2

Intel-specific functions:
Version 00000f24:
Type 0 - Original OEM
Family 15 - Pentium 4
Extended family 0
Model 2 - 
Stepping 4
Reserved 0

Brand index: 9 [not in table]
Extended brand string: "              Intel(R) Pentium(R) 4 CPU 2.00GHz"
CLFLUSH instruction cache line size: 8
Hyper threading siblings: 1

Feature flags 3febfbff:
FPU    Floating Point Unit
VME    Virtual 8086 Mode Enhancements
DE     Debugging Extensions
PSE    Page Size Extensions
TSC    Time Stamp Counter
MSR    Model Specific Registers
PAE    Physical Address Extension
MCE    Machine Check Exception
CX8    COMPXCHG8B Instruction
APIC   On-chip Advanced Programmable Interrupt Controller present and enabled
SEP    Fast System Call
MTRR   Memory Type Range Registers
PGE    PTE Global Flag
MCA    Machine Check Architecture
CMOV   Conditional Move and Compare Instructions
FGPAT  Page Attribute Table
PSE-36 36-bit Page Size Extension
CLFSH  CFLUSH instruction
DS     Debug store
ACPI   Thermal Monitor and Clock Ctrl
MMX    MMX instruction set
FXSR   Fast FP/MMX Streaming SIMD Extensions save/restore
SSE    Streaming SIMD Extensions instruction set
SSE2   SSE2 extensions
SS     Self Snoop
HT     Hyper Threading
TM     Thermal monitor

TLB and cache info:
50: Instruction TLB: 4KB and 2MB or 4MB pages, 64 entries
5b: Data TLB: 4KB and 4MB pages, 64 entries
66: 1st-level data cache: 8KB, 4-way set assoc, 64 byte line size
40: No 2nd-level cache, or if 2nd-level cache exists, no 3rd-level cache
70: Trace cache: 12K-micro-op, 4-way set assoc
7b: 2nd-level cache: 512KB, 8-way set assoc, sectored, 64 byte line size


Stefan