A registerised mips-linux port of GHC

[Simon Marlow]

Thiemo Seufer wrote:
> Hello All,
> 
> I currently try to get a ghc port on mips-linux going. I understand
> Igloo does the same ATM, and things look promising so far.
> 
> However, the port is currently unregisterised, and I would like to
> improve it a bit. A registerised port seems to be achievable with
> a moderate amount of work. I looked a bit around in the code, and
> have now a few questions:
> 
> - The example of other ports suggests the useful maximum of general
>   purpose registers for GHC is 8. I also presume that unmentioned
>   registers aren't touched by haskell code. Is this correct?

In MachRegs.h you specify registers that are globally reserved for use by 
Haskell code, such as the stack or heap pointer.  Other registers are still 
available for use as normal by gcc or the native code generator.

The R1-R8 registers are for argument-passing and returning unboxed tuples.  R1 
is by far the most important, you *must* put R1 in a register to get any kind of 
reasonable performance.  It's a bit sad that we have to globally reserve 
registers for argument passing, but that's the way it is right now.  The native 
code generator could actually make much better use of these registers than it 
currently does.

> - The comments in the source suggest that callee-saved registers are
>   preferable, without further explanation. I would expect a mix of
>   caller- and callee-saved registers to be potentially better. Any
>   advice on this?

The only reason that callee-saves registers are better is because they don't 
have to be saved and restored around an FFI call.  If you're going to use 
caller-saves registers, then use them for R2-R8, because those registers don't 
always have to be saved, since we know when they contain live data.  For 
example, if you put Hp or Sp in a caller-saves register, these would need to be 
saved around *every* FFI call, since they are always live.

> - The mips ABI defines 8 (or 9 when including the frame pointer)
>   registers as callee-saved, and more than 9 caller-saved temporaries.
>   With four registers taken for stack/heap pointers this leaves a
>   5/3 split of callee-saved/caller-saved registers, if all my
>   assumptions above are ok. Are there other considerations to take
>   into account for the register layout?

With 5/3, I suggest putting R1-R4 in callee-saves and R5-R8 in caller-saves. 
what about floating point regs?

Cheers,
	Simon