[GHC] #5506: LLVM AST : needs an LlvmType ctor to represent vectors so that LLVM can generate SIMD instructions

[GHC]

#5506: LLVM AST : needs an LlvmType ctor to represent vectors so that LLVM can
generate SIMD instructions
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    Reporter:  erikd             |       Owner:  dterei         
        Type:  task              |      Status:  patch          
    Priority:  normal            |   Component:  Compiler (LLVM)
     Version:  7.3               |    Keywords:                 
    Testcase:                    |   Blockedby:                 
          Os:  Unknown/Multiple  |    Blocking:                 
Architecture:  Unknown/Multiple  |     Failure:  None/Unknown   
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Comment(by erikd):

 Replying to [comment:6 dterei]:
 > As for the vector 11 size example. Is the poor performance when the
 vector isn't length that is multiple of the native vector size?

 This one. It needs to be an integer multiple of the native vector size.

-- 
Ticket URL: <http://hackage.haskell.org/trac/ghc/ticket/5506#comment:7>
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