[GHC] #3557: CPU Vector instructions in GHC.Prim

[Alexander McPhail]

Hi,

In LLVM we can use the `<vector 4 float>` type


> > -- in StgCmmPrim.hs
> > translateOp Float4AddOp    = Just (MO_F_Add  W32_4)
>
>
[#llvm <irc://irc.oftc.net/%23llvm>] LLVM: Low Level Virtual Machine:
http://llvm.org/
> Hi, if I apply '%res = fadd <vector 4 float> %arg0 %arg1' on an SSE2
capable machine, will that `fadd` instruction generate operations that work
in the XMM 128 bit register?
> i get "addps %xmm1, %xmm0" for that
> nicholas: Awesome, that's an SSE instruction. Thanks for your help.

and it will generate SSE instructions for us.

Vivian

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