[GHC] #3557: CPU Vector instructions in GHC.Prim (was: SIMD operations in GHC.Prim)

[GHC]

#3557: CPU Vector instructions in GHC.Prim
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    Reporter:  guest             |        Owner:  vivian      
        Type:  feature request   |       Status:  new         
    Priority:  normal            |    Milestone:  _|_         
   Component:  Compiler (NCG)    |      Version:  6.11        
    Keywords:                    |     Testcase:              
   Blockedby:                    |   Difficulty:  Unknown     
          Os:  Unknown/Multiple  |     Blocking:              
Architecture:  Unknown/Multiple  |      Failure:  None/Unknown
---------------------------------+------------------------------------------

Comment(by guest):

 In the meantime I have learned that there is a difference between Vector
 and SIMD computing. The main difference is a 'shuffle' operation, that
 allows to permute vector elements. Thus SSE and Altivec vector computing,
 GPU's of Nvidia and ATI are SIMD. This proposal is about Vector Computing.
 See "The Perils of Parallel: Larrabee vs. Nvidia, MIMD vs. SIMD"
 http://perilsofparallel.blogspot.com/2008/09/larrabee-vs-nvidia-mimd-vs-
 simd.html
 I have changed the ticket name accordingly.

-- 
Ticket URL: <http://hackage.haskell.org/trac/ghc/ticket/3557#comment:6>
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