[GHC] #3557: CPU Vector instructions in GHC.Prim

[GHC]

#3557: CPU Vector instructions in GHC.Prim
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    Reporter:  guest             |        Owner:  vivian      
        Type:  feature request   |       Status:  new         
    Priority:  normal            |    Milestone:  _|_         
   Component:  Compiler (NCG)    |      Version:  6.11        
    Keywords:                    |     Testcase:              
   Blockedby:                    |   Difficulty:  Unknown     
          Os:  Unknown/Multiple  |     Blocking:              
Architecture:  Unknown/Multiple  |      Failure:  None/Unknown
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Comment(by vivian):

 Replying to [comment:26 guest]:
 > I do not know what Wikipedia pages are relevant for you, but I think
 > http://en.wikipedia.org/wiki/Vector_processor
 > supports the view, that SSE and AltiVec are about vector computing (or
 vector processing) not about parallel/SIMD computing.

 Quoting from the Wikipedia article linked above:

 ''Today, most commodity CPUs implement architectures that feature
 instructions for some vector processing on multiple (vectorized) data
 sets, typically known as SIMD (Single Instruction, Multiple Data). Common
 examples include MMX, SSE, and AltiVec.''

-- 
Ticket URL: <http://hackage.haskell.org/trac/ghc/ticket/3557#comment:28>
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