[GHC] #3557: CPU Vector instructions in GHC.Prim

[GHC]

#3557: CPU Vector instructions in GHC.Prim
---------------------------------+------------------------------------------
    Reporter:  guest             |        Owner:  vivian      
        Type:  feature request   |       Status:  new         
    Priority:  normal            |    Milestone:  _|_         
   Component:  Compiler (NCG)    |      Version:  6.11        
    Keywords:                    |     Testcase:              
   Blockedby:                    |   Difficulty:  Unknown     
          Os:  Unknown/Multiple  |     Blocking:              
Architecture:  Unknown/Multiple  |      Failure:  None/Unknown
---------------------------------+------------------------------------------

Comment(by vivian):

 Both GNU C, __attribute__((vector_size(n))), and LLVM, <vector n type>,
 support low-level packed types.

 I have primOps like:
 {{{
 unPack4FloatOp# :: FloatPacked4# -> (# Float#, Float#, Float#, Float# #)
 pack4FloatOp#   :: Float# -> Float# -> Float# -> Float# -> FloatPacked4#
 }}}

 and I have added corresponding `Widths` : {{{ W32 | ... | W32_4 | W64_2
 }}}

 At the Cmm level, I want to combine 4 floats into one 128-bit packed
 register.  (C and LLVM have operations for this, as does SSE).

 I'm not clear whether this should be new `CmmStmt` data constructors
 (`CmmPack | CmmUnPack`) or implemented as `CallishMachOps`.  Since we have
 the new `Width`s it seems that the right solution is to extend `CmmStmt`.

 It is also possible to achieve packing/unpacking with memory reads/writes
 and explicit casting.

-- 
Ticket URL: <http://hackage.haskell.org/trac/ghc/ticket/3557#comment:20>
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