[GHC] #14251: LLVM Code Gen messes up registers

[GHC]

#14251: LLVM Code Gen messes up registers
-------------------------------------+-------------------------------------
        Reporter:  angerman          |                Owner:  kavon
            Type:  bug               |               Status:  new
        Priority:  highest           |            Milestone:  8.6.2
       Component:  Compiler (LLVM)   |              Version:  8.3
      Resolution:                    |             Keywords:
Operating System:  Unknown/Multiple  |         Architecture:
 Type of failure:  Incorrect result  |  Unknown/Multiple
  at runtime                         |            Test Case:
      Blocked By:                    |             Blocking:
 Related Tickets:                    |  Differential Rev(s):  Phab:D5190
       Wiki Page:                    |
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Comment (by Ben Gamari <ben@…>):

 In [changeset:"d8495549ba9d194815c2d0eaee6797fc7c00756a/ghc" d849554/ghc]:
 {{{
 #!CommitTicketReference repository="ghc"
 revision="d8495549ba9d194815c2d0eaee6797fc7c00756a"
 Fix for T14251 on ARM

 We now calculate the SSE register padding needed to fix the calling
 convention in LLVM in a robust way: grouping them by whether
 registers in that class overlap (with the same class overlapping
 itself).

 My prior patch assumed that no matter the platform, physical
 register Fx aliases with Dx, etc, for our calling convention.

 This is unfortunately not the case for any platform except x86-64.

 Test Plan:
 Only know how to test on x86-64, but it should be tested on ARM with:

 `make test WAYS=llvm && make test WAYS=optllvm`

 Reviewers: bgamari, angerman

 Reviewed By: bgamari

 Subscribers: rwbarton, carter

 GHC Trac Issues: #15780, #14251, #15747

 Differential Revision: https://phabricator.haskell.org/D5254
 }}}

-- 
Ticket URL: <http://ghc.haskell.org/trac/ghc/ticket/14251#comment:25>
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