[GHC] #15124: Improve block layout for the NCG

[GHC]

#15124: Improve block layout for the NCG
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        Reporter:  AndreasK          |                Owner:  (none)
            Type:  task              |               Status:  new
        Priority:  normal            |            Milestone:  8.6.1
       Component:  Compiler (NCG)    |              Version:  8.2.2
      Resolution:                    |             Keywords:  CodeGen
Operating System:  Unknown/Multiple  |         Architecture:
                                     |  Unknown/Multiple
 Type of failure:  None/Unknown      |            Test Case:
      Blocked By:                    |             Blocking:
 Related Tickets:                    |  Differential Rev(s):
       Wiki Page:                    |
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Comment (by AndreasK):

 Besides the usual (Aigner Guides, Intel Optimization Manuals) here are a
 few more references which should make a good starting point to explore
 this space:

 [1] Thomas Ball, James R. Larus. Branch Prediction for Free (https://do
 i.org/10.1145/173262.155119)

 [2] Hans Wennborg. The recent switch lowering improvements. (http://llv
 m.org/devmtg/2015-10/slides/Wennborg-SwitchLowering.pdf) See also: http
 s://www.youtube.com/watch?v=gMqSinyL8uk

 [3] James E. Smith. A study of branch prediction strategies (https://dl
 .acm.org/citation.cfm?id=801871)

 [4] http://llvm.org/doxygen/MachineBlockPlacement_8cpp_source.html

 [5] Karl Pettis, Robert C. Hansen. Profile guided code positioning. (ht
 tps://doi.org/10.1145/93542.93550)

 [6] Hashemi et al. Efficient procedure mapping using cache line
 coloring (https://doi.org/10.1145/258915.258931)

-- 
Ticket URL: <http://ghc.haskell.org/trac/ghc/ticket/15124#comment:1>
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