[GHC] #14244: ghc-prim: hs_atomicread* and hs_atomicwrite* missing barriers

[GHC]

#14244: ghc-prim: hs_atomicread* and hs_atomicwrite* missing barriers
-------------------------------------+-------------------------------------
           Reporter:  trommler       |             Owner:  (none)
               Type:  bug            |            Status:  new
           Priority:  normal         |         Milestone:
          Component:  Prelude        |           Version:  8.2.1
           Keywords:                 |  Operating System:  Unknown/Multiple
       Architecture:                 |   Type of failure:  Incorrect result
  Unknown/Multiple                   |  at runtime
          Test Case:                 |        Blocked By:
           Blocking:                 |   Related Tickets:  #12537
Differential Rev(s):                 |         Wiki Page:
-------------------------------------+-------------------------------------
 The comments in `compiler/prelude/primops.txt.pp` for both operations say
 "... Implies a full memory barrier."

 The implementation does not issue any barriers as exemplified by the
 32-bit variants as can be seen in the excerpts from `libraries/ghc-
 prim/cbits/atomic.c`.
 {{{#!c
 StgWord
 hs_atomicread32(StgWord x)
 {
   return *(volatile StgWord32 *) x;
 }
 }}}
 and
 {{{#!c
 void
 hs_atomicwrite32(StgWord x, StgWord val)
 {
   *(volatile StgWord32 *) x = (StgWord32) val;
 }
 }}}

 The native code generator for X86/amd64 and the LLVM backend do not
 generate calls to these functions but generate the necessary barrier
 (`mfence`) directly and thus are not affected by this issue.

 There are no gcc `__sync_*` intrinsics for the two operations. The new
 `__atomic_*` intrinisics have the required operations but require gcc 4.7
 or later.

-- 
Ticket URL: <http://ghc.haskell.org/trac/ghc/ticket/14244>
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