[GHC] #13852: Can we have more SIMD primops, corresponding to the untapped AVX etc. instructions?

[GHC]

#13852: Can we have more SIMD primops, corresponding to the untapped AVX etc.
instructions?
-------------------------------------+-------------------------------------
        Reporter:  leftaroundabout   |                Owner:  (none)
            Type:  feature request   |               Status:  new
        Priority:  normal            |            Milestone:
       Component:  Compiler (LLVM)   |              Version:  8.0.1
      Resolution:                    |             Keywords:
Operating System:  Unknown/Multiple  |         Architecture:  x86_64
                                     |  (amd64)
 Type of failure:  None/Unknown      |            Test Case:
      Blocked By:                    |             Blocking:
 Related Tickets:                    |  Differential Rev(s):
       Wiki Page:                    |
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Comment (by hsyl20):

 Primitive operations on vectors are named `Vec*` in
 [https://github.com/ghc/ghc/blob/b1fa386cdae1af45fdd3519014be850f83414ab3/compiler/prelude/primops.txt.pp#L2994
 prelude/primops.txt.pp] (e.g, `VecDivOp`). The genprimopcode utility
 generates a primop per vector type and width. For instance in
 compiler/stage1/build/primop-list.hs-incl:

 {{{
    , (VecDivOp FloatVec 4 W32)
    , (VecDivOp FloatVec 2 W64)
    , (VecDivOp FloatVec 8 W32)
    , (VecDivOp FloatVec 4 W64)
    , (VecDivOp FloatVec 16 W32)
    , (VecDivOp FloatVec 8 W64)
 }}}

 These are converted from Stg to Cmm by `translateOp` in
 [https://github.com/ghc/ghc/blob/b1fa386cdae1af45fdd3519014be850f83414ab3/compiler/codeGen/StgCmmPrim.hs#L1245
 codeGen/StgCmmPrim.hs]. For instance, `VecDivOp FloatVec` becomes
 `MO_VF_Quot`.

 Then you need to use the LLVM backend to convert Cmm into LLVM (textual)
 IR. This is done by `genMachOp_slow` in
 [https://github.com/ghc/ghc/blob/b1fa386cdae1af45fdd3519014be850f83414ab3/compiler/llvmGen/LlvmCodeGen/CodeGen.hs#L1367
 llvmGen/LlvmCodeGen/CodeGen.hs].

 Finally LLVM generates the assembly and GHC
 [https://github.com/ghc/ghc/blob/b1fa386cdae1af45fdd3519014be850f83414ab3/compiler/llvmGen/LlvmMangler.hs
 replaces some instructions] because it can't guarantee that the alignment
 is correct. Note that the native code generator don't support them yet:
 you have to use the LLVM backend.

 If the instructions you want are supported by LLVM, they should be
 relatively easy to add.

--
Ticket URL: <http://ghc.haskell.org/trac/ghc/ticket/13852#comment:3>
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