[GHC] #7741: Add SIMD support to x86/x86_64 NCG

[GHC]

#7741: Add SIMD support to x86/x86_64 NCG
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        Reporter:  shelarcy          |                Owner:  (none)
            Type:  feature request   |               Status:  new
        Priority:  normal            |            Milestone:
       Component:  Compiler (NCG)    |              Version:  7.7
      Resolution:                    |             Keywords:  SIMD
Operating System:  Unknown/Multiple  |         Architecture:
 Type of failure:  Runtime           |  Unknown/Multiple
  performance bug                    |            Test Case:
      Blocked By:                    |             Blocking:
 Related Tickets:  #3557             |  Differential Rev(s):
       Wiki Page:  wiki:SIMD         |
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Comment (by bgamari):

 In response to recent interest in SIMD support, I pondered this for a bit
 while wandering in the woods yesterday. I think there's a pretty
 straightforward path to introducing SIMD (including AVX) support in the
 NCG. Here's my proposed plan,

  * Introduce a few types,
    {{{#!hs
    -- | The format of a vector value
    data VecFormat = VecFormat { vecWidth  :: Width  -- ^ vector width
 (e.g. how many scalars?)
                               , vecFormat :: ScalarFormat -- ^ the format
 of each scalar
                               }
    -- | What type of quantity is a scalar?
    data ScalarFormat = FmtInt | FmtFloat
    -- | The width of a scalar in bits
    data ScalarWidth = Width8 | Width16 | Width32 | Width64

    -- this already exists
    type Width = Int
    }}}
  * Rework the instructions in `nativeGen/X86/Instr.hs` to carry a
 `VecFormat` instead of a `Format`. Perhaps just start with `ADD` before
 moving on to the others just to make sure this plan works.
  * For the purposes for register allocation pretend there are only ZMM
 registers (e.g. ignoring XMM and YMM). This saves us from having to worry
 about register aliasing. We can then use the `VecFormat` to determine what
 kind of register we really mean. I believe this can be done in
 `nativeGen/X86/Regs.hs:allocatableRegs`.
  * I think the calling convention logic (e.g. in `cmm/CmmCallConv.hs`)
 should require no change.
  * Add the necessary pretty-printing logic (in `nativeGen/X86/Ppr.hs`) to
 produce the new instructions
  * Add the necessary logic to the code generator to implement the
 `MachOps` (e.g. `nativeGen/X86/CodeGen.hs`)

 All-in-all this seems quite feasible and likely no more than a day or two
 of work.

--
Ticket URL: <http://ghc.haskell.org/trac/ghc/ticket/7741#comment:13>
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