[GHC] #12469: Memory fence on writes to MutVar/Array missing on ARM

[GHC]

#12469: Memory fence on writes to MutVar/Array missing on ARM
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        Reporter:  rrnewton          |                Owner:
            Type:  bug               |               Status:  patch
        Priority:  normal            |            Milestone:  8.0.2
       Component:  Compiler          |              Version:  8.0.1
      Resolution:                    |             Keywords:  memory model
Operating System:  Unknown/Multiple  |         Architecture:
 Type of failure:  Incorrect result  |  Unknown/Multiple
  at runtime                         |            Test Case:
      Blocked By:                    |             Blocking:  12537
 Related Tickets:                    |  Differential Rev(s):  Phab:D2495
       Wiki Page:                    |  Phab:D2525
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Comment (by trommler):

 Replying to [comment:25 simonmar]:
 > If a `sync` fixes it then that would be a useful data point.  If not, it
 means there are barriers missing elsewhere.
 Using `sync` the situation improves a lot on my PowerMac G5 quad. `Setup
 build -j4` still segfaults randomly but only occasionally. With `lwsync`
 it almost always segfaulted. An improvement but not a fix.

 So I read the Power ISA specification again (especially Book II, Appendix
 B Programming Examples for Sharing Storage): It seems that even a `sync`
 on processor A is not sufficient to prevent reordering of loads on
 processor B. A load-load barrier is required when there is no data
 dependency between the two loads. I will look into that option over the
 weekend.

--
Ticket URL: <http://ghc.haskell.org/trac/ghc/ticket/12469#comment:26>
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