[GHC] #12469: Memory fence on writeIORef missing on ARM

[GHC]

#12469: Memory fence on writeIORef missing on ARM
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        Reporter:  rrnewton          |                Owner:
            Type:  bug               |               Status:  patch
        Priority:  normal            |            Milestone:  8.2.1
       Component:  Compiler          |              Version:  8.0.1
      Resolution:                    |             Keywords:  memory model
Operating System:  Unknown/Multiple  |         Architecture:
                                     |  Unknown/Multiple
 Type of failure:  None/Unknown      |            Test Case:
      Blocked By:                    |             Blocking:
 Related Tickets:                    |  Differential Rev(s):  Phab:D2495
       Wiki Page:                    |
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Comment (by rrnewton):

 That looks like the right kind of thing, but it needs to be conditional --
 only on the ARM backend.  We wouldn't want to slow down x86.

 Ideally, it would only apply in `-threaded` mode to boot, but my current
 understanding is that we only make the distinction at the final link phase
 (which runtime to link), not as a different "way" during compilation.

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Ticket URL: <http://ghc.haskell.org/trac/ghc/ticket/12469#comment:7>
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