[GHC] #9350: Consider using xchg instead of mfence for CS stores

[GHC]

#9350: Consider using xchg instead of mfence for CS stores
-------------------------------------+-------------------------------------
       Reporter:  tibbe              |                   Owner:
           Type:  feature request    |                  Status:  new
       Priority:  normal             |               Milestone:
      Component:  Compiler           |                 Version:  7.9
       Keywords:                     |        Operating System:
   Architecture:  Unknown/Multiple   |  Unknown/Multiple
     Difficulty:  Easy (less than 1  |         Type of failure:
  hour)                              |  None/Unknown
     Blocked By:                     |               Test Case:
Related Tickets:                     |                Blocking:
                                     |  Differential Revisions:
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 To get sequential consistency for `atomicWriteIntArray#` we use an
 `mfence` instruction. An alternative is to use an `xchg` instruction
 (which has an implicit `lock` prefix), which might have lower latency.  We
 should check what other compilers do.

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Ticket URL: <http://ghc.haskell.org/trac/ghc/ticket/9350>
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