[GHC] #8033: add AVX register support to llvm calling convention
GHC
ghc-devs at haskell.org
Wed Jul 3 04:26:34 CEST 2013
#8033: add AVX register support to llvm calling convention
-----------------------------+----------------------------------------------
Reporter: carter | Owner:
Type: feature request | Status: new
Priority: normal | Component: Compiler
Version: 7.7 | Keywords:
Os: Unknown/Multiple | Architecture: Unknown/Multiple
Failure: None/Unknown | Blockedby:
Blocking: | Related:
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GHC HEAD currently has support for SSE 128bit registers (XMM), and it
would be very little additional work to add 256bit AVX2 operations (when
available) PROVIDED that the llvm calling convention for ghc is modified
to support them when available
the current definition in LLVM can be seen here https://github.com/llvm-
mirror/llvm/blob/master/lib/Target/X86/X86CallingConv.td#L279-L291
the current definition is
{{{
def CC_X86_64_GHC : CallingConv<[
// Promote i8/i16/i32 arguments to i64.
CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
// Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim
CCIfType<[i64],
CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9,
R15]>>,
// Pass in STG registers: F1, F2, F3, F4, D1, D2
CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
CCIfSubtarget<"hasSSE1()",
CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>,
]>;
}}}
I believe the update should read
{{{
def CC_X86_64_GHC : CallingConv<[
// Promote i8/i16/i32 arguments to i64.
CCIfType<[i8, i16, i32], CCPromoteToType<i64>>,
// Pass in STG registers: Base, Sp, Hp, R1, R2, R3, R4, R5, R6, SpLim
CCIfType<[i64],
CCAssignToReg<[R13, RBP, R12, RBX, R14, RSI, RDI, R8, R9,
R15]>>,
// Pass in STG registers for floats,doubles and 128bit simd vectors
CCIfType<[f32, f64, v16i8, v8i16, v4i32, v2i64, v4f32, v2f64],
CCIfSubtarget<"hasSSE1()",
CCAssignToReg<[XMM1, XMM2, XMM3, XMM4, XMM5, XMM6]>>>,
// Pass in STG registers for first 7 256bit simd vectors
CCIfType<[v32i8, v16i16, v8i32, v4i64, v8f32, v4f64],
CCIfSubtarget<"hasAVX()",
CCAssignToReg<[YMM0, YMM1, YMM2, YMM3,
YMM4, YMM5, YMM6]>>>
]>;
}}}
Note that this is FULLY backwards compatible with current GHC, it merely
means that we can have 256bit simd values if we so choose.
if I get the go ahead from y'all, i'm happy to see about getting that
patch into llvm
--
Ticket URL: <http://hackage.haskell.org/trac/ghc/ticket/8033>
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