[Git][ghc/ghc][wip/supersven/riscv-vectors] Cleanup warnings
Sven Tennie (@supersven)
gitlab at gitlab.haskell.org
Mon Mar 10 17:57:41 UTC 2025
Sven Tennie pushed to branch wip/supersven/riscv-vectors at Glasgow Haskell Compiler / GHC
Commits:
bd98351d by Sven Tennie at 2025-03-10T18:57:24+01:00
Cleanup warnings
- - - - -
4 changed files:
- compiler/CodeGen.Platform.h
- compiler/GHC/CmmToAsm/RV64/CodeGen.hs
- compiler/GHC/CmmToAsm/RV64/Instr.hs
- compiler/GHC/CmmToAsm/RV64/Ppr.hs
Changes:
=====================================
compiler/CodeGen.Platform.h
=====================================
@@ -1274,44 +1274,6 @@ freeReg REG_XMM5 = False
freeReg REG_XMM6 = False
# endif
-# if defined(REG_YMM1)
-freeReg REG_YMM1 = False
-# endif
-# if defined(REG_YMM2)
-freeReg REG_YMM2 = False
-# endif
-# if defined(REG_YMM3)
-freeReg REG_YMM3 = False
-# endif
-# if defined(REG_YMM4)
-freeReg REG_YMM4 = False
-# endif
-# if defined(REG_YMM5)
-freeReg REG_YMM5 = False
-# endif
-# if defined(REG_YMM6)
-freeReg REG_YMM6 = False
-# endif
-
-# if defined(REG_ZMM1)
-freeReg REG_ZMM1 = False
-# endif
-# if defined(REG_ZMM2)
-freeReg REG_ZMM2 = False
-# endif
-# if defined(REG_ZMM3)
-freeReg REG_ZMM3 = False
-# endif
-# if defined(REG_ZMM4)
-freeReg REG_ZMM4 = False
-# endif
-# if defined(REG_ZMM5)
-freeReg REG_ZMM5 = False
-# endif
-# if defined(REG_ZMM6)
-freeReg REG_ZMM6 = False
-# endif
-
freeReg _ = True
#else
=====================================
compiler/GHC/CmmToAsm/RV64/CodeGen.hs
=====================================
@@ -1107,7 +1107,6 @@ getRegister' config plat expr =
| fitsIn12bitImm n ->
return $ Any toFmt (\d -> unitOL $ annExpr expr (ORI (OpReg toFmt d) (OpReg fromFmt r') (OpImm (ImmInteger n))))
where
- w' = formatToWidth (cmmTypeFormat (cmmRegType reg))
r' = getRegisterReg plat reg
toFmt = intFormat w
fromFmt = (cmmTypeFormat (cmmRegType reg))
@@ -1274,8 +1273,8 @@ getRegister' config plat expr =
MO_S_Shr w -> intOp True w (\d x y -> unitOL $ annExpr expr (SRA d x y))
-- Vector operations
- MO_VF_Extract length w -> vecExtract ((scalarFormatFormat . floatScalarFormat) w)
- MO_V_Extract length w -> vecExtract ((scalarFormatFormat . intScalarFormat) w)
+ MO_VF_Extract _length w -> vecExtract ((scalarFormatFormat . floatScalarFormat) w)
+ MO_V_Extract _length w -> vecExtract ((scalarFormatFormat . intScalarFormat) w)
MO_VF_Add length w -> vecOp (floatVecFormat length w) VADD
MO_VF_Sub length w -> vecOp (floatVecFormat length w) VSUB
@@ -1433,7 +1432,7 @@ getRegister' config plat expr =
-- Return 0 when the operation cannot overflow, /= 0 otherwise
do_mul_may_oflo :: Width -> CmmExpr -> CmmExpr -> NatM Register
do_mul_may_oflo w _x _y | w > W64 = pprPanic "Cannot multiply larger than 64bit" (ppr w)
- do_mul_may_oflo w at W64 x y = do
+ do_mul_may_oflo W64 x y = do
(reg_x, format_x, code_x) <- getSomeReg x
(reg_y, format_y, code_y) <- getSomeReg y
-- TODO: Can't we clobber reg_x and reg_y to save registers?
@@ -1762,12 +1761,12 @@ genCondJump ::
genCondJump bid expr = do
case expr of
-- Optimized == 0 case.
- CmmMachOp (MO_Eq w) [x, CmmLit (CmmInt 0 _)] -> do
+ CmmMachOp (MO_Eq _w) [x, CmmLit (CmmInt 0 _)] -> do
(reg_x, format_x, code_x) <- getSomeReg x
return $ code_x `snocOL` annExpr expr (BCOND EQ zero (OpReg format_x reg_x) (TBlock bid))
-- Optimized /= 0 case.
- CmmMachOp (MO_Ne w) [x, CmmLit (CmmInt 0 _)] -> do
+ CmmMachOp (MO_Ne _w) [x, CmmLit (CmmInt 0 _)] -> do
(reg_x, format_x, code_x) <- getSomeReg x
return $ code_x `snocOL` annExpr expr (BCOND NE zero (OpReg format_x reg_x) (TBlock bid))
@@ -1811,8 +1810,8 @@ genCondJump bid expr = do
`appOL` unitOL (annExpr expr (BCOND cmp x' y' (TBlock bid)))
_ -> code_x `appOL` code_y `appOL` unitOL (annExpr expr (BCOND cmp x' y' (TBlock bid)))
- fbcond :: Width -> Cond -> NatM (OrdList Instr)
- fbcond w cmp = do
+ fbcond :: Cond -> NatM (OrdList Instr)
+ fbcond cmp = do
-- ensure we get float regs
(reg_fx, format_fx, code_fx) <- getFloatReg x
(reg_fy, format_fy, code_fy) <- getFloatReg y
@@ -1825,12 +1824,12 @@ genCondJump bid expr = do
`snocOL` BCOND EQ condOpReg (OpReg II64 oneReg) (TBlock bid)
case mop of
- MO_F_Eq w -> fbcond w EQ
- MO_F_Ne w -> fbcond w NE
- MO_F_Gt w -> fbcond w FGT
- MO_F_Ge w -> fbcond w FGE
- MO_F_Lt w -> fbcond w FLT
- MO_F_Le w -> fbcond w FLE
+ MO_F_Eq _w -> fbcond EQ
+ MO_F_Ne _w -> fbcond NE
+ MO_F_Gt _w -> fbcond FGT
+ MO_F_Ge _w -> fbcond FGE
+ MO_F_Lt _w -> fbcond FLT
+ MO_F_Le _w -> fbcond FLE
MO_Eq w -> sbcond w EQ
MO_Ne w -> sbcond w NE
MO_S_Gt w -> sbcond w SGT
@@ -2029,7 +2028,7 @@ genCCall target@(ForeignTarget expr _cconv) dest_regs arg_regs = do
passArguments gpRegs fpRegs vRegs args stackSpaceWords (vReg : accumRegs) accumCode'
-- No more vector regs, and we want to pass a vector argument.
- passArguments gpRegs fpRegs (vReg : vRegs) ((r, format, _hint, code_r) : args) stackSpaceWords accumRegs accumCode
+ passArguments _gpRegs _fpRegs (_vReg : _vRegs) ((_r, format, _hint, _code_r) : _args) _stackSpaceWords _accumRegs _accumCode
| isVecFormat format =
pprPanic "passArguments" (text "TODO: Implement and test vector argument passing on the stack.")
passArguments _ _ _ _ _ _ _ = pprPanic "passArguments" (text "invalid state")
@@ -2217,7 +2216,7 @@ genCCall (PrimTarget mop) dest_regs arg_regs = do
format = intFormat w
return code
| otherwise -> panic "mal-formed AtomicRead"
- mo@(MO_AtomicWrite w ord)
+ mo@(MO_AtomicWrite _w ord)
| [p_reg, val_reg] <- arg_regs -> do
(p, _fmt_p, code_p) <- getSomeReg p_reg
(val, fmt_val, code_val) <- getSomeReg val_reg
=====================================
compiler/GHC/CmmToAsm/RV64/Instr.hs
=====================================
@@ -20,7 +20,6 @@ import GHC.CmmToAsm.Utils
import GHC.Data.FastString (LexicalFastString)
import GHC.Platform
import GHC.Platform.Reg
-import GHC.Platform.Reg.Class.Separate
import GHC.Platform.Regs
import GHC.Prelude
import GHC.Stack
=====================================
compiler/GHC/CmmToAsm/RV64/Ppr.hs
=====================================
@@ -797,7 +797,7 @@ pprInstr platform instr = case instr of
FNMSub -> text "\tfnmsub" <> dot <> floatPrecission d
in op4 fma d r1 r2 r3
VFMA variant o1@(OpReg fmt _reg) o2 o3
- | VecFormat l fmt' <- fmt ->
+ | VecFormat _l fmt' <- fmt ->
let formatString = if (isFloatFormat . scalarFormatFormat) fmt' then text "f" else text ""
prefix = text "v" <> formatString
suffix = text "vv"
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/commit/bd98351dc047e8714b8265cd803e48e06c666188
--
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/commit/bd98351dc047e8714b8265cd803e48e06c666188
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