[Git][ghc/ghc][wip/hadrian-cross-stage2] 3 commits: Fix regArch for riscv64
Matthew Pickering (@mpickering)
gitlab at gitlab.haskell.org
Mon Sep 30 14:57:14 UTC 2024
Matthew Pickering pushed to branch wip/hadrian-cross-stage2 at Glasgow Haskell Compiler / GHC
Commits:
2cf41cd5 by Matthew Pickering at 2024-09-30T14:56:57+01:00
Fix regArch for riscv64
The register allocator doesn't support vector registers on riscv64,
therefore advertise as NoVectors.
- - - - -
6e0385a2 by Matthew Pickering at 2024-09-30T15:13:13+01:00
riscv: Avoid using csrr instruction to test for vector registers
The csrr instruction isn't allowed in qemu user-mode, and raises an
illegal instruction error when it is encountered.
Therefore for now, we just hard-code that there is no support for vector
registers since the rest of the compiler doesn't support vector
registers for riscv.
Fixes #25312
- - - - -
c6cdccbe by Andreas Klebinger at 2024-09-30T15:20:20+01:00
Add support for fp min/max to riscv
Fixes #25313
- - - - -
5 changed files:
- compiler/GHC/CmmToAsm/RV64/CodeGen.hs
- compiler/GHC/CmmToAsm/RV64/Instr.hs
- compiler/GHC/CmmToAsm/RV64/Ppr.hs
- compiler/GHC/Platform/Reg/Class.hs
- rts/CheckVectorSupport.c
Changes:
=====================================
compiler/GHC/CmmToAsm/RV64/CodeGen.hs
=====================================
@@ -1109,6 +1109,8 @@ getRegister' config plat expr =
MO_F_Mul w -> floatOp w (\d x y -> unitOL $ annExpr expr (MUL d x y))
MO_F_Quot w -> floatOp w (\d x y -> unitOL $ annExpr expr (DIV d x y))
-- Floating point comparison
+ MO_F_Min w -> floatOp w (\d x y -> unitOL $ annExpr expr (FMIN d x y))
+ MO_F_Max w -> floatOp w (\d x y -> unitOL $ annExpr expr (FMAX d x y))
MO_F_Eq w -> floatCond w (\d x y -> unitOL $ annExpr expr (CSET d x y EQ))
MO_F_Ne w -> floatCond w (\d x y -> unitOL $ annExpr expr (CSET d x y NE))
MO_F_Ge w -> floatCond w (\d x y -> unitOL $ annExpr expr (CSET d x y FGE))
@@ -2208,6 +2210,8 @@ makeFarBranches {- only used when debugging -} _platform statics basic_blocks =
FENCE {} -> 1
FCVT {} -> 1
FABS {} -> 1
+ FMIN {} -> 1
+ FMAX {} -> 1
FMA {} -> 1
-- estimate the subsituted size for jumps to lables
-- jumps to registers have size 1
=====================================
compiler/GHC/CmmToAsm/RV64/Instr.hs
=====================================
@@ -107,6 +107,8 @@ regUsageOfInstr platform instr = case instr of
FENCE _ _ -> usage ([], [])
FCVT _variant dst src -> usage (regOp src, regOp dst)
FABS dst src -> usage (regOp src, regOp dst)
+ FMIN dst src1 src2 -> usage (regOp src1 ++ regOp src2, regOp dst)
+ FMAX dst src1 src2 -> usage (regOp src1 ++ regOp src2, regOp dst)
FMA _ dst src1 src2 src3 ->
usage (regOp src1 ++ regOp src2 ++ regOp src3, regOp dst)
_ -> panic $ "regUsageOfInstr: " ++ instrCon instr
@@ -203,6 +205,8 @@ patchRegsOfInstr instr env = case instr of
FENCE o1 o2 -> FENCE o1 o2
FCVT variant o1 o2 -> FCVT variant (patchOp o1) (patchOp o2)
FABS o1 o2 -> FABS (patchOp o1) (patchOp o2)
+ FMIN o1 o2 o3 -> FMIN (patchOp o1) (patchOp o2) (patchOp o3)
+ FMAX o1 o2 o3 -> FMAX (patchOp o1) (patchOp o2) (patchOp o3)
FMA s o1 o2 o3 o4 ->
FMA s (patchOp o1) (patchOp o2) (patchOp o3) (patchOp o4)
_ -> panic $ "patchRegsOfInstr: " ++ instrCon instr
@@ -603,6 +607,13 @@ data Instr
FCVT FcvtVariant Operand Operand
| -- | Floating point ABSolute value
FABS Operand Operand
+
+ | -- | Min
+ -- dest = min(r1)
+ FMIN Operand Operand Operand
+ | -- | Max
+ FMAX Operand Operand Operand
+
| -- | Floating-point fused multiply-add instructions
--
-- - fmadd : d = r1 * r2 + r3
@@ -658,6 +669,8 @@ instrCon i =
FENCE {} -> "FENCE"
FCVT {} -> "FCVT"
FABS {} -> "FABS"
+ FMIN {} -> "FMIN"
+ FMAX {} -> "FMAX"
FMA variant _ _ _ _ ->
case variant of
FMAdd -> "FMADD"
=====================================
compiler/GHC/CmmToAsm/RV64/Ppr.hs
=====================================
@@ -666,6 +666,10 @@ pprInstr platform instr = case instr of
$ line (pprOp platform o1 <> text "->" <> pprOp platform o2)
FABS o1 o2 | isSingleOp o2 -> op2 (text "\tfabs.s") o1 o2
FABS o1 o2 | isDoubleOp o2 -> op2 (text "\tfabs.d") o1 o2
+ FMIN o1 o2 o3 | isSingleOp o1 -> op3 (text "\tfmin.s") o1 o2 o3
+ | isDoubleOp o2 -> op3 (text "\tfmin.d") o1 o2 o3
+ FMAX o1 o2 o3 | isSingleOp o1 -> op3 (text "\tfmax.s") o1 o2 o3
+ | isDoubleOp o2 -> op3 (text "\tfmax.d") o1 o2 o3
FMA variant d r1 r2 r3 ->
let fma = case variant of
FMAdd -> text "\tfmadd" <> dot <> floatPrecission d
=====================================
compiler/GHC/Platform/Reg/Class.hs
=====================================
@@ -49,5 +49,8 @@ registerArch arch =
ArchPPC -> Unified
ArchPPC_64 {} -> Unified
ArchAArch64 -> Unified
- ArchRISCV64 -> Separate
+ -- Support for vector registers not yet implemented for RISC-V
+ -- see panic in `getFreeRegs`.
+ --ArchRISCV64 -> Separate
+ ArchRISCV64 -> NoVectors
_ -> NoVectors
=====================================
rts/CheckVectorSupport.c
=====================================
@@ -65,12 +65,16 @@ int checkVectorSupport(void) {
*/
#elif defined(__riscv)
- unsigned long vlenb;
- asm volatile ("csrr %0, vlenb" : "=r" (vlenb));
+// csrr instruction nott allowed in user-mode qemu emulation of riscv
+// Backend doesn't yet support vector registers, so hard-coded to no vector support
+// for now.
+//
+// unsigned long vlenb;
+// asm volatile ("csrr %0, vlenb" : "=r" (vlenb));
// VLENB gives the length in bytes
- supports_V16 = vlenb >= 16;
- supports_V32 = vlenb >= 32;
- supports_V64 = vlenb >= 64;
+ supports_V16 = 0;
+ supports_V32 = 0;
+ supports_V64 = 0;
#else
// On other platforms, we conservatively return no vector support.
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/compare/a22ee5c462ca1e2c9d08404b4d62181eb60e6dac...c6cdccbe9843350f35a55169cb2d97f3e48dd1bf
--
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/compare/a22ee5c462ca1e2c9d08404b4d62181eb60e6dac...c6cdccbe9843350f35a55169cb2d97f3e48dd1bf
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