[Git][ghc/ghc][wip/marge_bot_batch_merge_job] 20 commits: The X86 SIMD patch.
Marge Bot (@marge-bot)
gitlab at gitlab.haskell.org
Tue Sep 24 04:24:04 UTC 2024
Marge Bot pushed to branch wip/marge_bot_batch_merge_job at Glasgow Haskell Compiler / GHC
Commits:
b6c8783d by sheaf at 2024-09-24T00:23:37-04:00
The X86 SIMD patch.
This commit adds support for 128 bit wide SIMD vectors and vector
operations to GHC's X86 native code generator.
Main changes:
- Introduction of vector formats (`GHC.CmmToAsm.Format`)
- Introduction of 128-bit virtual register (`GHC.Platform.Reg`),
and removal of unused Float virtual register.
- Refactor of `GHC.Platform.Reg.Class.RegClass`: it now only contains
two classes, `RcInteger` (for general purpose registers) and `RcFloatOrVector`
(for registers that can be used for scalar floating point values as well
as vectors).
- Modify `GHC.CmmToAsm.X86.Instr.regUsageOfInstr` to keep track
of which format each register is used at, so that the register
allocator can know if it needs to spill the entire vector register
or just the lower 64 bits.
- Modify spill/load/reg-2-reg code to account for vector registers
(`GHC.CmmToAsm.X86.Instr.{mkSpillInstr, mkLoadInstr, mkRegRegMoveInstr, takeRegRegMoveInstr}`).
- Modify the register allocator code (`GHC.CmmToAsm.Reg.*`) to propagate
the format we are storing in any given register, for instance changing
`Reg` to `RegFormat` or `GlobalReg` to `GlobalRegUse`.
- Add logic to lower vector `MachOp`s to X86 assembly
(see `GHC.CmmToAsm.X86.CodeGen`)
- Minor cleanups to genprimopcode, to remove the llvm_only attribute
which is no longer applicable.
Tests for this feature are provided in the "testsuite/tests/simd" directory.
Fixes #7741
Keeping track of register formats adds a small memory overhead to the
register allocator (in particular, regUsageOfInstr now allocates more
to keep track of the `Format` each register is used at). This explains
the following metric increases.
-------------------------
Metric Increase:
T12707
T13035
T13379
T3294
T4801
T5321FD
T5321Fun
T783
-------------------------
- - - - -
195cc08d by sheaf at 2024-09-24T00:23:37-04:00
Use xmm registers in genapply
This commit updates genapply to use xmm, ymm and zmm registers, for
stg_ap_v16/stg_ap_v32/stg_ap_v64, respectively.
It also updates the Cmm lexer and parser to produce Cmm vectors rather
than 128/256/512 bit wide scalars for V16/V32/V64, removing bits128,
bits256 and bits512 in favour of vectors.
The Cmm Lint check is weakened for vectors, as (in practice, e.g. on X86)
it is okay to use a single vector register to hold multiple different
types of data, and we don't know just from seeing e.g. "XMM1" how to
interpret the 128 bits of data within.
Fixes #25062
- - - - -
a1b40531 by sheaf at 2024-09-24T00:23:37-04:00
Add vector fused multiply-add operations
This commit adds fused multiply add operations such as `fmaddDoubleX2#`.
These are handled both in the X86 NCG and the LLVM backends.
- - - - -
27fdfbbb by sheaf at 2024-09-24T00:23:38-04:00
Add vector shuffle primops
This adds vector shuffle primops, such as
```
shuffleFloatX4# :: FloatX4# -> FloatX4# -> (# Int#, Int#, Int#, Int# #) -> FloatX4#
```
which shuffle the components of the input two vectors into the output vector.
NB: the indices must be compile time literals, to match the X86 SHUFPD
instruction immediate and the LLVM shufflevector instruction.
These are handled in the X86 NCG and the LLVM backend.
Tested in simd009.
- - - - -
1991af34 by sheaf at 2024-09-24T00:23:38-04:00
Add Broadcast MachOps
This adds proper MachOps for broadcast instructions, allowing us to
produce better code for broadcasting a value than simply packing that
value (doing many vector insertions in a row).
These are lowered in the X86 NCG and LLVM backends. In the LLVM backend,
it uses the previously introduced shuffle instructions.
- - - - -
1d1a265e by sheaf at 2024-09-24T00:23:38-04:00
Fix treatment of signed zero in vector negation
This commit fixes the handling of signed zero in floating-point vector
negation.
A slight hack was introduced to work around the fact that Cmm doesn't
currently have a notion of signed floating point literals
(see get_float_broadcast_value_reg). This can be removed once CmmFloat
can express the value -0.0.
The simd006 test has been updated to use a stricter notion of equality
of floating-point values, which ensure the validity of this change.
- - - - -
a11a15fa by sheaf at 2024-09-24T00:23:38-04:00
Add min/max primops
This commit adds min/max primops, such as
minDouble# :: Double# -> Double# -> Double#
minFloatX4# :: FloatX4# -> FloatX4# -> FloatX4#
minWord16X8# :: Word16X8# -> Word16X8# -> Word16X8#
These are supported in:
- the X86, AArch64 and PowerPC NCGs,
- the LLVM backend,
- the WebAssembly and JavaScript backends.
Fixes #25120
- - - - -
032b2e01 by sheaf at 2024-09-24T00:23:38-04:00
Add test for C calls & SIMD vectors
- - - - -
e2e3c619 by sheaf at 2024-09-24T00:23:38-04:00
Add test for #25169
- - - - -
805cf1bf by sheaf at 2024-09-24T00:23:38-04:00
Fix #25169 using Plan A from the ticket
We now compile certain low-level Cmm functions in the RTS multiple
times, with different levels of vector support. We then dispatch
at runtime in the RTS, based on what instructions are supported.
See Note [realArgRegsCover] in GHC.Cmm.CallConv.
Fixes #25169
-------------------------
Metric Increase:
T10421
T12425
T1969
T9198
-------------------------
- - - - -
5cca7265 by sheaf at 2024-09-24T00:23:38-04:00
Fix C calls with SIMD vectors
This commit fixes the code generation for C calls, to take into account
the calling convention.
This is particularly tricky on Windows, where all vectors are expected
to be passed by reference. See Note [The Windows X64 C calling convention]
in GHC.CmmToAsm.X86.CodeGen.
- - - - -
73093d86 by sheaf at 2024-09-24T00:23:38-04:00
X86 CodeGen: refactor getRegister CmmLit
This refactors the code dealing with loading literals into registers,
removing duplication and putting all the code in a single place.
It also changes which XOR instruction is used to place a zero value
into a register, so that we use VPXOR for a 128-bit integer vector
when AVX is supported.
- - - - -
eb482a39 by sheaf at 2024-09-24T00:23:38-04:00
X86 genCCall: promote arg before calling evalArgs
The job of evalArgs is to ensure each argument is put into a temporary
register, so that it can then be loaded directly into one of the
argument registers for the C call, without the generated code clobbering
any other register used for argument passing.
However, if we promote arguments after calling evalArgs, there is the
possibility that the code used for the promotion will clobber a register,
defeating the work of evalArgs.
To avoid this, we first promote arguments, and only then call evalArgs.
- - - - -
f37664a5 by sheaf at 2024-09-24T00:23:38-04:00
X86 genCCall64: simplify loadArg code
This commit simplifies the argument loading code by making the
assumption that it is safe to directly load the argument into register,
because doing so will not clobber any previous assignments.
This assumption is borne from the use of 'evalArgs', which evaluates
any arguments which might necessitate non-trivial code generation into
separate temporary registers.
- - - - -
1bfe3e2e by sheaf at 2024-09-24T00:23:38-04:00
LLVM: propagate GlobalRegUse information
This commit ensures we keep track of how any particular global register
is being used in the LLVM backend. This informs the LLVM type
annotations, and avoids type mismatches of the following form:
argument is not of expected type '<2 x double>'
call ccc <2 x double> (<2 x double>)
(<4 x i32> arg)
- - - - -
c1b8b91a by Brandon Chinn at 2024-09-24T00:23:39-04:00
Replace manual string lexing (#25158)
Metric Increase:
MultilineStringsPerf
- - - - -
82b09fc9 by ARATA Mizuki at 2024-09-24T00:23:42-04:00
Document primitive string literals and desugaring of string literals
Fixes #17474 and #17974
Co-authored-by: Matthew Craven <5086-clyring at users.noreply.gitlab.haskell.org>
- - - - -
5cc10e20 by Hécate Kleidukos at 2024-09-24T00:23:48-04:00
Add setup for tags generation
This commit creates a top-level Makefile and a configuration file for
the ghc-tags program.
closes #25239
- - - - -
9fbb2087 by Simon Peyton Jones at 2024-09-24T00:23:48-04:00
Improve GHC.Tc.Solver.defaultEquality
This MR improves GHC.Tc.Solver.defaultEquality to solve #25251.
The main change is to use checkTyEqRhs to check the equality, so
that we do promotion properly.
But within that we needed a small enhancement to LC_Promote. See
Note [Defaulting equalites] (DE4) and (DE5)
The tricky case is (alas) hard to trigger, so I have not added a
regression test.
- - - - -
ced2b207 by Alan Zimmerman at 2024-09-24T00:23:49-04:00
EPA: Remove unused hsCaseAnnsRest
We never populate it, so remove it.
- - - - -
30 changed files:
- .gitignore
- + Makefile
- compiler/GHC/Builtin/primops.txt.pp
- compiler/GHC/ByteCode/Asm.hs
- compiler/GHC/Cmm.hs
- compiler/GHC/Cmm/CallConv.hs
- compiler/GHC/Cmm/Graph.hs
- compiler/GHC/Cmm/Lexer.x
- compiler/GHC/Cmm/Lint.hs
- compiler/GHC/Cmm/Liveness.hs
- compiler/GHC/Cmm/MachOp.hs
- compiler/GHC/Cmm/Node.hs
- compiler/GHC/Cmm/Opt.hs
- compiler/GHC/Cmm/Parser.y
- compiler/GHC/Cmm/ProcPoint.hs
- compiler/GHC/Cmm/Reg.hs
- compiler/GHC/Cmm/Sink.hs
- compiler/GHC/Cmm/Type.hs
- compiler/GHC/CmmToAsm.hs
- compiler/GHC/CmmToAsm/AArch64.hs
- compiler/GHC/CmmToAsm/AArch64/CodeGen.hs
- compiler/GHC/CmmToAsm/AArch64/Instr.hs
- compiler/GHC/CmmToAsm/AArch64/Ppr.hs
- compiler/GHC/CmmToAsm/AArch64/Regs.hs
- compiler/GHC/CmmToAsm/Config.hs
- compiler/GHC/CmmToAsm/Format.hs
- compiler/GHC/CmmToAsm/Instr.hs
- compiler/GHC/CmmToAsm/PPC.hs
- compiler/GHC/CmmToAsm/PPC/CodeGen.hs
- compiler/GHC/CmmToAsm/PPC/Instr.hs
The diff was not included because it is too large.
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/compare/6985e5669ce660fb4ad315025e0fc305317a6057...ced2b20725ba965f8ea2ae3ff494d9b162fdef6f
--
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/compare/6985e5669ce660fb4ad315025e0fc305317a6057...ced2b20725ba965f8ea2ae3ff494d9b162fdef6f
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