[Git][ghc/ghc][wip/supersven/riscv64-ncg] 12 commits: Beauify allMachRegNos
Sven Tennie (@supersven)
gitlab at gitlab.haskell.org
Tue Mar 5 20:00:39 UTC 2024
Sven Tennie pushed to branch wip/supersven/riscv64-ncg at Glasgow Haskell Compiler / GHC
Commits:
9a8af3a2 by Sven Tennie at 2024-03-05T12:48:43+01:00
Beauify allMachRegNos
- - - - -
a6af09dc by Sven Tennie at 2024-03-05T13:10:03+01:00
Delete unused function strImmLit
- - - - -
569330e5 by Sven Tennie at 2024-03-05T14:48:36+01:00
Introduce constant firstFpRegNo
Makes usages more readable.
- - - - -
a5908d00 by Sven Tennie at 2024-03-05T15:24:53+01:00
Add TODOs
- - - - -
1c707282 by Sven Tennie at 2024-03-05T18:30:06+01:00
Cleanup register constants
- - - - -
952c4ab0 by Sven Tennie at 2024-03-05T19:19:50+01:00
Make reg numbers less magic
- - - - -
d5e9df2c by Sven Tennie at 2024-03-05T19:32:56+01:00
More on RegNo
- - - - -
84e5bb2a by Sven Tennie at 2024-03-05T19:38:03+01:00
Improve comment
- - - - -
73ab87ca by Sven Tennie at 2024-03-05T20:08:34+01:00
Remove unused / non-existent addressing mode
- - - - -
1ad87d41 by Sven Tennie at 2024-03-05T20:10:02+01:00
Reformat / cleanup
- - - - -
9805cb59 by Sven Tennie at 2024-03-05T20:11:35+01:00
Add TODOs
- - - - -
da053cea by Sven Tennie at 2024-03-05T20:57:54+01:00
More on RegNos
- - - - -
4 changed files:
- compiler/GHC/CmmToAsm/RV64/CodeGen.hs
- compiler/GHC/CmmToAsm/RV64/Instr.hs
- compiler/GHC/CmmToAsm/RV64/Ppr.hs
- compiler/GHC/CmmToAsm/RV64/Regs.hs
Changes:
=====================================
compiler/GHC/CmmToAsm/RV64/CodeGen.hs
=====================================
@@ -502,7 +502,7 @@ getRegister' config plat expr =
CmmLit lit ->
case lit of
- CmmInt 0 w -> pure $ Fixed (intFormat w) zero_reg nilOL
+ CmmInt 0 w -> pure $ Fixed (intFormat w) zeroReg nilOL
CmmInt i w ->
-- narrowU is important: Negative immediates may be
-- sign-extended on load!
@@ -1762,8 +1762,8 @@ genCCall target dest_regs arg_regs bid = do
if hint == SignedHint
then
code_r
- `appOL` signExtend w W64 r ip_reg
- `snocOL` ann (text "Pass signed argument (size " <> ppr w <> text ") on the stack: " <> ppr ip_reg) str
+ `appOL` signExtend w W64 r ipReg
+ `snocOL` ann (text "Pass signed argument (size " <> ppr w <> text ") on the stack: " <> ppr ipReg) str
else
code_r
`snocOL` ann (text "Pass unsigned argument (size " <> ppr w <> text ") on the stack: " <> ppr r) str
=====================================
compiler/GHC/CmmToAsm/RV64/Instr.hs
=====================================
@@ -161,7 +161,6 @@ regUsageOfInstr platform instr = case instr of
(filter (interesting platform) dst)
regAddr :: AddrMode -> [Reg]
- regAddr (AddrRegReg r1 r2) = [r1, r2]
regAddr (AddrRegImm r1 _) = [r1]
regAddr (AddrReg r1) = [r1]
regOp :: Operand -> [Reg]
@@ -205,12 +204,12 @@ regUsageOfInstr platform instr = case instr of
-- ZR: Zero, RA: Return Address, SP: Stack Pointer, GP: Global Pointer, TP: Thread Pointer, FP: Frame Pointer
-- BR: Base, SL: SpLim
callerSavedRegisters :: [Reg]
-callerSavedRegisters
- = map regSingle [5..7]
- ++ map regSingle [10..17]
- ++ map regSingle [28..31]
- ++ map regSingle [32..39]
- ++ map regSingle [42..49]
+callerSavedRegisters =
+ map regSingle [t0RegNo .. t2RegNo]
+ ++ map regSingle [a0RegNo .. a7RegNo]
+ ++ map regSingle [t3RegNo .. t6RegNo]
+ ++ map regSingle [ft0RegNo .. ft7RegNo]
+ ++ map regSingle [fa0RegNo .. fa7RegNo]
-- | Apply a given mapping to all the register references in this
-- instruction.
@@ -302,7 +301,6 @@ patchRegsOfInstr instr env = case instr of
patchTarget (TReg r) = TReg (env r)
patchTarget t = t
patchAddr :: AddrMode -> AddrMode
- patchAddr (AddrRegReg r1 r2) = AddrRegReg (env r1) (env r2)
patchAddr (AddrRegImm r1 i) = AddrRegImm (env r1) i
patchAddr (AddrReg r) = AddrReg (env r)
--------------------------------------------------------------------------------
@@ -388,12 +386,12 @@ mkSpillInstr config reg delta slot =
]
where
fmt = case reg of
- RegReal (RealRegSingle n) | n < 32 -> II64
+ RegReal (RealRegSingle n) | n < d0RegNo -> II64
_ -> FF64
- mkStrSpImm imm = ANN (text "Spill@" <> int (off - delta)) $ STR fmt (OpReg W64 reg) (OpAddr (AddrRegImm sp_reg (ImmInt imm)))
+ mkStrSpImm imm = ANN (text "Spill@" <> int (off - delta)) $ STR fmt (OpReg W64 reg) (OpAddr (AddrRegImm spMachReg (ImmInt imm)))
movImmToIp imm = ANN (text "Spill: IP <- " <> int imm) $ MOV ip (OpImm (ImmInt imm))
addSpToIp = ANN (text "Spill: IP <- SP + IP ") $ ADD ip ip sp
- mkStrIp = ANN (text "Spill@" <> int (off - delta)) $ STR fmt (OpReg W64 reg) (OpAddr (AddrReg ip_reg))
+ mkStrIp = ANN (text "Spill@" <> int (off - delta)) $ STR fmt (OpReg W64 reg) (OpAddr (AddrReg ipReg))
off = spillSlotToOffset slot
@@ -414,12 +412,12 @@ mkLoadInstr _config reg delta slot =
]
where
fmt = case reg of
- RegReal (RealRegSingle n) | n < 32 -> II64
+ RegReal (RealRegSingle n) | n < d0RegNo -> II64
_ -> FF64
- mkLdrSpImm imm = ANN (text "Reload@" <> int (off - delta)) $ LDR fmt (OpReg W64 reg) (OpAddr (AddrRegImm sp_reg (ImmInt imm)))
+ mkLdrSpImm imm = ANN (text "Reload@" <> int (off - delta)) $ LDR fmt (OpReg W64 reg) (OpAddr (AddrRegImm spMachReg (ImmInt imm)))
movImmToIp imm = ANN (text "Reload: IP <- " <> int imm) $ MOV ip (OpImm (ImmInt imm))
addSpToIp = ANN (text "Reload: IP <- SP + IP ") $ ADD ip ip sp
- mkLdrIp = ANN (text "Reload@" <> int (off - delta)) $ LDR fmt (OpReg W64 reg) (OpAddr (AddrReg ip_reg))
+ mkLdrIp = ANN (text "Reload@" <> int (off - delta)) $ LDR fmt (OpReg W64 reg) (OpAddr (AddrReg ipReg))
off = spillSlotToOffset slot
@@ -795,10 +793,6 @@ data Operand
| OpAddr AddrMode -- memory reference
deriving (Eq, Show)
--- Smart constructors
-opReg :: Width -> Reg -> Operand
-opReg = OpReg
-
-- Note [The made-up RISCV64 IP register]
-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
--
@@ -817,98 +811,101 @@ opReg = OpReg
-- X31 is a caller-saved register. I.e. there are no guarantees about what the
-- callee does with it. That's exactly what we want here.
-zero_reg, ra_reg, sp_reg, ip_reg :: Reg
-zero_reg = RegReal (RealRegSingle 0)
-ra_reg = RegReal (RealRegSingle 1)
-sp_reg = RegReal (RealRegSingle 2)
-ip_reg = RegReal (RealRegSingle 31)
+zeroReg, raReg, spMachReg, ipReg :: Reg
+zeroReg = regSingle 0
+raReg = regSingle 1
+-- | Not to be confused with the `CmmReg` `spReg`
+spMachReg = regSingle 2
+ipReg = regSingle 31
+
+operandFromReg :: Reg -> Operand
+operandFromReg = OpReg W64
+
+operandFromRegNo :: RegNo -> Operand
+operandFromRegNo = operandFromReg . regSingle
zero, ra, sp, gp, tp, fp, ip :: Operand
-zero = OpReg W64 zero_reg
-ra = OpReg W64 ra_reg
-sp = OpReg W64 sp_reg
-gp = OpReg W64 (RegReal (RealRegSingle 3))
-tp = OpReg W64 (RegReal (RealRegSingle 4))
-fp = OpReg W64 (RegReal (RealRegSingle 8))
-ip = OpReg W64 ip_reg
-
-_x :: Int -> Operand
-_x i = OpReg W64 (RegReal (RealRegSingle i))
+zero = operandFromReg zeroReg
+ra = operandFromReg raReg
+sp = operandFromReg spMachReg
+gp = operandFromRegNo 3
+tp = operandFromRegNo 4
+fp = operandFromRegNo 8
+ip = operandFromReg ipReg
+
x0, x1, x2, x3, x4, x5, x6, x7 :: Operand
x8, x9, x10, x11, x12, x13, x14, x15 :: Operand
x16, x17, x18, x19, x20, x21, x22, x23 :: Operand
x24, x25, x26, x27, x28, x29, x30, x31 :: Operand
-x0 = OpReg W64 (RegReal (RealRegSingle 0))
-x1 = OpReg W64 (RegReal (RealRegSingle 1))
-x2 = OpReg W64 (RegReal (RealRegSingle 2))
-x3 = OpReg W64 (RegReal (RealRegSingle 3))
-x4 = OpReg W64 (RegReal (RealRegSingle 4))
-x5 = OpReg W64 (RegReal (RealRegSingle 5))
-x6 = OpReg W64 (RegReal (RealRegSingle 6))
-x7 = OpReg W64 (RegReal (RealRegSingle 7))
-x8 = OpReg W64 (RegReal (RealRegSingle 8))
-x9 = OpReg W64 (RegReal (RealRegSingle 9))
-x10 = OpReg W64 (RegReal (RealRegSingle 10))
-x11 = OpReg W64 (RegReal (RealRegSingle 11))
-x12 = OpReg W64 (RegReal (RealRegSingle 12))
-x13 = OpReg W64 (RegReal (RealRegSingle 13))
-x14 = OpReg W64 (RegReal (RealRegSingle 14))
-x15 = OpReg W64 (RegReal (RealRegSingle 15))
-x16 = OpReg W64 (RegReal (RealRegSingle 16))
-x17 = OpReg W64 (RegReal (RealRegSingle 17))
-x18 = OpReg W64 (RegReal (RealRegSingle 18))
-x19 = OpReg W64 (RegReal (RealRegSingle 19))
-x20 = OpReg W64 (RegReal (RealRegSingle 20))
-x21 = OpReg W64 (RegReal (RealRegSingle 21))
-x22 = OpReg W64 (RegReal (RealRegSingle 22))
-x23 = OpReg W64 (RegReal (RealRegSingle 23))
-x24 = OpReg W64 (RegReal (RealRegSingle 24))
-x25 = OpReg W64 (RegReal (RealRegSingle 25))
-x26 = OpReg W64 (RegReal (RealRegSingle 26))
-x27 = OpReg W64 (RegReal (RealRegSingle 27))
-x28 = OpReg W64 (RegReal (RealRegSingle 28))
-x29 = OpReg W64 (RegReal (RealRegSingle 29))
-x30 = OpReg W64 (RegReal (RealRegSingle 30))
-x31 = OpReg W64 (RegReal (RealRegSingle 31))
-
-_d :: Int -> Operand
-_d = OpReg W64 . RegReal . RealRegSingle
+x0 = operandFromRegNo x0RegNo
+x1 = operandFromRegNo 1
+x2 = operandFromRegNo 2
+x3 = operandFromRegNo 3
+x4 = operandFromRegNo 4
+x5 = operandFromRegNo x5RegNo
+x6 = operandFromRegNo 6
+x7 = operandFromRegNo x7RegNo
+x8 = operandFromRegNo 8
+x9 = operandFromRegNo 9
+x10 = operandFromRegNo x10RegNo
+x11 = operandFromRegNo 11
+x12 = operandFromRegNo 12
+x13 = operandFromRegNo 13
+x14 = operandFromRegNo 14
+x15 = operandFromRegNo 15
+x16 = operandFromRegNo 16
+x17 = operandFromRegNo x17RegNo
+x18 = operandFromRegNo 18
+x19 = operandFromRegNo 19
+x20 = operandFromRegNo 20
+x21 = operandFromRegNo 21
+x22 = operandFromRegNo 22
+x23 = operandFromRegNo 23
+x24 = operandFromRegNo 24
+x25 = operandFromRegNo 25
+x26 = operandFromRegNo 26
+x27 = operandFromRegNo 27
+x28 = operandFromRegNo x28RegNo
+x29 = operandFromRegNo 29
+x30 = operandFromRegNo 30
+x31 = operandFromRegNo x31RegNo
+
d0, d1, d2, d3, d4, d5, d6, d7 :: Operand
d8, d9, d10, d11, d12, d13, d14, d15 :: Operand
d16, d17, d18, d19, d20, d21, d22, d23 :: Operand
d24, d25, d26, d27, d28, d29, d30, d31 :: Operand
-d0 = OpReg W64 (RegReal (RealRegSingle 32))
-d1 = OpReg W64 (RegReal (RealRegSingle 33))
-d2 = OpReg W64 (RegReal (RealRegSingle 34))
-d3 = OpReg W64 (RegReal (RealRegSingle 35))
-d4 = OpReg W64 (RegReal (RealRegSingle 36))
-d5 = OpReg W64 (RegReal (RealRegSingle 37))
-d6 = OpReg W64 (RegReal (RealRegSingle 38))
-d7 = OpReg W64 (RegReal (RealRegSingle 39))
-d8 = OpReg W64 (RegReal (RealRegSingle 40))
-d9 = OpReg W64 (RegReal (RealRegSingle 41))
-d10 = OpReg W64 (RegReal (RealRegSingle 42))
-d11 = OpReg W64 (RegReal (RealRegSingle 43))
-d12 = OpReg W64 (RegReal (RealRegSingle 44))
-d13 = OpReg W64 (RegReal (RealRegSingle 45))
-d14 = OpReg W64 (RegReal (RealRegSingle 46))
-d15 = OpReg W64 (RegReal (RealRegSingle 47))
-d16 = OpReg W64 (RegReal (RealRegSingle 48))
-d17 = OpReg W64 (RegReal (RealRegSingle 49))
-d18 = OpReg W64 (RegReal (RealRegSingle 50))
-d19 = OpReg W64 (RegReal (RealRegSingle 51))
-d20 = OpReg W64 (RegReal (RealRegSingle 52))
-d21 = OpReg W64 (RegReal (RealRegSingle 53))
-d22 = OpReg W64 (RegReal (RealRegSingle 54))
-d23 = OpReg W64 (RegReal (RealRegSingle 55))
-d24 = OpReg W64 (RegReal (RealRegSingle 56))
-d25 = OpReg W64 (RegReal (RealRegSingle 57))
-d26 = OpReg W64 (RegReal (RealRegSingle 58))
-d27 = OpReg W64 (RegReal (RealRegSingle 59))
-d28 = OpReg W64 (RegReal (RealRegSingle 60))
-d29 = OpReg W64 (RegReal (RealRegSingle 61))
-d30 = OpReg W64 (RegReal (RealRegSingle 62))
-d31 = OpReg W64 (RegReal (RealRegSingle 63))
+d0 = operandFromRegNo d0RegNo
+d1 = operandFromRegNo 33
+d2 = operandFromRegNo 34
+d3 = operandFromRegNo 35
+d4 = operandFromRegNo 36
+d5 = operandFromRegNo 37
+d6 = operandFromRegNo 38
+d7 = operandFromRegNo d7RegNo
+d8 = operandFromRegNo 40
+d9 = operandFromRegNo 41
+d10 = operandFromRegNo d10RegNo
+d11 = operandFromRegNo 43
+d12 = operandFromRegNo 44
+d13 = operandFromRegNo 45
+d14 = operandFromRegNo 46
+d15 = operandFromRegNo 47
+d16 = operandFromRegNo 48
+d17 = operandFromRegNo d17RegNo
+d18 = operandFromRegNo 50
+d19 = operandFromRegNo 51
+d20 = operandFromRegNo 52
+d21 = operandFromRegNo 53
+d22 = operandFromRegNo 54
+d23 = operandFromRegNo 55
+d24 = operandFromRegNo 56
+d25 = operandFromRegNo 57
+d26 = operandFromRegNo 58
+d27 = operandFromRegNo 59
+d28 = operandFromRegNo 60
+d29 = operandFromRegNo 61
+d30 = operandFromRegNo 62
+d31 = operandFromRegNo d31RegNo
opRegSExt :: Width -> Reg -> Operand
opRegSExt W64 r = OpRegExt W64 r ESXTX 0
@@ -981,7 +978,8 @@ makeFarBranches info_env blocks
-- 262144 (2^20 / 4) instructions are allowed; let's keep some distance, as
-- we have pseudo-insns that are pretty-printed as multiple instructions,
- -- and it's just not worth the effort to calculate things exactly. The
+ -- and it's just not worth the effort to calculate things exactly as linker
+ -- relaxations are applied later (optimizing away our flaws.) The
-- conservative guess here is that every instruction does not emit more than
-- two in the mean.
nearLimit = 131072 - mapSize info_env * maxRetInfoTableSizeW
=====================================
compiler/GHC/CmmToAsm/RV64/Ppr.hs
=====================================
@@ -304,6 +304,7 @@ negOp (OpImm (ImmInt i)) = OpImm (ImmInt (negate i))
negOp (OpImm (ImmInteger i)) = OpImm (ImmInteger (negate i))
negOp op = pprPanic "RV64.negOp" (text $ show op)
+-- TODO: Is this used in RISCV?!
pprExt :: IsLine doc => ExtMode -> doc
pprExt EUXTB = text "uxtb"
pprExt EUXTH = text "uxth"
@@ -314,6 +315,7 @@ pprExt ESXTH = text "sxth"
pprExt ESXTW = text "sxtw"
pprExt ESXTX = text "sxtx"
+-- TODO: Is this used in RISCV?!
pprShift :: IsLine doc => ShiftMode -> doc
pprShift SLSL = text "lsl"
pprShift SLSR = text "lsr"
@@ -328,8 +330,6 @@ pprOp plat op = case op of
OpRegShift w r s i -> pprReg w r <> comma <+> pprShift s <+> char '#' <> int i
OpImm im -> pprIm plat im
OpImmShift im s i -> pprIm plat im <> comma <+> pprShift s <+> char '#' <> int i
- -- TODO: Address computation always use registers as 64bit -- is this correct?
- OpAddr (AddrRegReg r1 r2) -> pprPanic "No Reg-Reg addressing mode in Riscv" (text $ show op) -- char '[' <+> pprReg W64 r1 <> comma <+> pprReg W64 r2 <+> char ']'
OpAddr (AddrRegImm r1 im) -> pprImm plat im <> char '(' <> pprReg W64 r1 <> char ')'
OpAddr (AddrReg r1) -> text "0(" <+> pprReg W64 r1 <+> char ')'
=====================================
compiler/GHC/CmmToAsm/RV64/Regs.hs
=====================================
@@ -16,42 +16,87 @@ import GHC.Utils.Outputable
import GHC.Utils.Panic
import GHC.Platform
+-- | First integer register number. @zero@ register.
+x0RegNo :: RegNo
+x0RegNo = 0
+
+x5RegNo, t0RegNo :: RegNo
+x5RegNo = 5
+t0RegNo = x5RegNo
+
+x7RegNo, t2RegNo :: RegNo
+x7RegNo = 7
+t2RegNo = x7RegNo
+
+x28RegNo, t3RegNo :: RegNo
+x28RegNo = 28
+t3RegNo = x28RegNo
+
+-- | Last integer register number. Used as IP register.
+x31RegNo, t6RegNo, ipRegNo :: RegNo
+x31RegNo = 31
+t6RegNo = x31RegNo
+ipRegNo = x31RegNo
+
+-- | First floating point register.
+d0RegNo, ft0RegNo :: RegNo
+d0RegNo = 32
+ft0RegNo = d0RegNo
+
+d7RegNo, ft7RegNo :: RegNo
+d7RegNo = 39
+ft7RegNo = d7RegNo
+
+-- | Last floating point register.
+d31RegNo :: RegNo
+d31RegNo = 63
+
+a0RegNo, x10RegNo :: RegNo
+x10RegNo = 10
+a0RegNo = x10RegNo
+
+a7RegNo, x17RegNo :: RegNo
+x17RegNo = 17
+a7RegNo = x17RegNo
+
+fa0RegNo, d10RegNo :: RegNo
+d10RegNo = 42
+fa0RegNo = d10RegNo
+
+fa7RegNo, d17RegNo :: RegNo
+d17RegNo = 49
+fa7RegNo = d17RegNo
+
+-- | All machine register numbers.
allMachRegNos :: [RegNo]
-allMachRegNos = [0 .. 31] ++ [32 .. 63]
+allMachRegNos = intRegs ++ fpRegs
+ where
+ intRegs = [x0RegNo .. x31RegNo]
+ fpRegs = [d0RegNo .. d31RegNo]
--- allocatableRegs is allMachRegNos with the fixed-use regs removed.
--- i.e., these are the regs for which we are prepared to allow the
--- register allocator to attempt to map VRegs to.
+-- | Registers available to the register allocator.
+--
+-- These are all registers minus those with a fixed role in RISCV ABI (zero, lr,
+-- sp, gp, tp, fp, ip) and GHC RTS (Base, Sp, Hp, HpLim, R1..R8, F1..F6,
+-- D1..D6.)
allocatableRegs :: Platform -> [RealReg]
-allocatableRegs platform
- = let isFree = freeReg platform
- in map RealRegSingle $ filter isFree allMachRegNos
+allocatableRegs platform =
+ let isFree = freeReg platform
+ in map RealRegSingle $ filter isFree allMachRegNos
--- argRegs is the set of regs which are read for an n-argument call to C.
+-- | Integer argument registers according to the calling convention
allGpArgRegs :: [Reg]
-allGpArgRegs = map regSingle [10..17]
-allFpArgRegs :: [Reg]
-allFpArgRegs = map regSingle [42..49]
-
--- STG:
--- 19: Base
--- 20: Sp
--- 21: Hp
--- 22-27: R1-R6
--- 28: SpLim
-
--- This is the STG Sp reg.
--- sp :: Reg
--- sp = regSingle 20
+allGpArgRegs = map regSingle [a0RegNo .. a7RegNo]
--- addressing modes ------------------------------------------------------------
+-- | Floating point argument registers according to the calling convention
+allFpArgRegs :: [Reg]
+allFpArgRegs = map regSingle [fa0RegNo .. fa7RegNo]
--- TODO: AddrRegReg constructor is never used. Remove it?
+-- | Addressing modes
data AddrMode
- = AddrRegReg Reg Reg
- | AddrRegImm Reg Imm
- | AddrReg Reg
- deriving (Eq, Show)
+ = AddrRegImm Reg Imm
+ | AddrReg Reg
+ deriving (Eq, Show)
-- -----------------------------------------------------------------------------
-- Immediates
@@ -68,25 +113,20 @@ data Imm
| ImmConstantDiff Imm Imm
deriving (Eq, Show)
-strImmLit :: FastString -> Imm
-strImmLit s = ImmLit s
-
-
litToImm :: CmmLit -> Imm
-litToImm (CmmInt i w) = ImmInteger (narrowS w i)
- -- narrow to the width: a CmmInt might be out of
- -- range, but we assume that ImmInteger only contains
- -- in-range values. A signed value should be fine here.
-litToImm (CmmFloat f W32) = ImmFloat f
-litToImm (CmmFloat f W64) = ImmDouble f
-litToImm (CmmLabel l) = ImmCLbl l
+litToImm (CmmInt i w) = ImmInteger (narrowS w i)
+-- narrow to the width: a CmmInt might be out of
+-- range, but we assume that ImmInteger only contains
+-- in-range values. A signed value should be fine here.
+litToImm (CmmFloat f W32) = ImmFloat f
+litToImm (CmmFloat f W64) = ImmDouble f
+litToImm (CmmLabel l) = ImmCLbl l
litToImm (CmmLabelOff l off) = ImmIndex l off
-litToImm (CmmLabelDiffOff l1 l2 off _)
- = ImmConstantSum
- (ImmConstantDiff (ImmCLbl l1) (ImmCLbl l2))
- (ImmInt off)
-litToImm _ = panic "RV64.Regs.litToImm: no match"
-
+litToImm (CmmLabelDiffOff l1 l2 off _) =
+ ImmConstantSum
+ (ImmConstantDiff (ImmCLbl l1) (ImmCLbl l2))
+ (ImmInt off)
+litToImm l = panic $ "RV64.Regs.litToImm: no match for " ++ show l
-- == To satisfy GHC.CmmToAsm.Reg.Target =======================================
@@ -116,21 +156,19 @@ virtualRegSqueeze cls vr
{-# INLINE realRegSqueeze #-}
realRegSqueeze :: RegClass -> RealReg -> Int
-realRegSqueeze cls rr
- = case cls of
- RcInteger
- -> case rr of
- RealRegSingle regNo
- | regNo < 32 -> 1 -- first fp reg is 32
- | otherwise -> 0
-
- RcDouble
- -> case rr of
- RealRegSingle regNo
- | regNo < 32 -> 0
- | otherwise -> 1
-
- _other -> 0
+realRegSqueeze cls rr =
+ case cls of
+ RcInteger ->
+ case rr of
+ RealRegSingle regNo
+ | regNo < d0RegNo -> 1
+ | otherwise -> 0
+ RcDouble ->
+ case rr of
+ RealRegSingle regNo
+ | regNo < d0RegNo -> 0
+ | otherwise -> 1
+ _other -> 0
mkVirtualReg :: Unique -> Format -> VirtualReg
mkVirtualReg u format
@@ -141,11 +179,11 @@ mkVirtualReg u format
FF64 -> VirtualRegD u
_ -> panic "RV64.mkVirtualReg"
-{-# INLINE classOfRealReg #-}
+{-# INLINE classOfRealReg #-}
classOfRealReg :: RealReg -> RegClass
classOfRealReg (RealRegSingle i)
- | i < 32 = RcInteger
- | otherwise = RcDouble
+ | i < d0RegNo = RcInteger
+ | otherwise = RcDouble
regDotColor :: RealReg -> SDoc
regDotColor reg
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/compare/9b73cf299516bd383b1f14baf073df100d1369dd...da053cea8d36f62887083575202a01da261dd492
--
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/compare/9b73cf299516bd383b1f14baf073df100d1369dd...da053cea8d36f62887083575202a01da261dd492
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