[Git][ghc/ghc][wip/ncg-simd] SIMD cleanups, remove virtual Float reg
sheaf (@sheaf)
gitlab at gitlab.haskell.org
Tue Jun 18 09:32:12 UTC 2024
sheaf pushed to branch wip/ncg-simd at Glasgow Haskell Compiler / GHC
Commits:
9ffe722e by sheaf at 2024-06-18T11:31:55+02:00
SIMD cleanups, remove virtual Float reg
- - - - -
10 changed files:
- compiler/GHC/CmmToAsm/AArch64/Ppr.hs
- compiler/GHC/CmmToAsm/AArch64/Regs.hs
- compiler/GHC/CmmToAsm/PPC/Ppr.hs
- compiler/GHC/CmmToAsm/PPC/Regs.hs
- compiler/GHC/CmmToAsm/Reg/Graph/TrivColorable.hs
- compiler/GHC/CmmToAsm/X86/CodeGen.hs
- compiler/GHC/CmmToAsm/X86/Instr.hs
- compiler/GHC/CmmToAsm/X86/Ppr.hs
- compiler/GHC/CmmToAsm/X86/Regs.hs
- compiler/GHC/Platform/Reg.hs
Changes:
=====================================
compiler/GHC/CmmToAsm/AArch64/Ppr.hs
=====================================
@@ -306,7 +306,6 @@ pprReg w r = case r of
RegReal (RealRegSingle i) -> ppr_reg_no w i
-- virtual regs should not show up, but this is helpful for debugging.
RegVirtual (VirtualRegI u) -> text "%vI_" <> pprUniqueAlways u
- RegVirtual (VirtualRegF u) -> text "%vF_" <> pprUniqueAlways u
RegVirtual (VirtualRegD u) -> text "%vD_" <> pprUniqueAlways u
_ -> pprPanic "AArch64.pprReg" (text $ show r)
@@ -336,8 +335,8 @@ pprReg w r = case r of
isFloatOp :: Operand -> Bool
isFloatOp (OpReg _ (RegReal (RealRegSingle i))) | i > 31 = True
-isFloatOp (OpReg _ (RegVirtual (VirtualRegF _))) = True
isFloatOp (OpReg _ (RegVirtual (VirtualRegD _))) = True
+-- SIMD NCG TODO: what about VirtualVecV128? Could be floating-point or not?
isFloatOp _ = False
pprInstr :: IsDoc doc => Platform -> Instr -> doc
=====================================
compiler/GHC/CmmToAsm/AArch64/Regs.hs
=====================================
@@ -111,7 +111,7 @@ virtualRegSqueeze cls vr
RcFloatOrVector
-> case vr of
VirtualRegD{} -> 1
- VirtualRegF{} -> 0
+ VirtualRegV128{} -> 1
_other -> 0
{-# INLINE realRegSqueeze #-}
=====================================
compiler/GHC/CmmToAsm/PPC/Ppr.hs
=====================================
@@ -199,7 +199,6 @@ pprReg r
RegReal (RealRegSingle i) -> ppr_reg_no i
RegVirtual (VirtualRegI u) -> text "%vI_" <> pprUniqueAlways u
RegVirtual (VirtualRegHi u) -> text "%vHi_" <> pprUniqueAlways u
- RegVirtual (VirtualRegF u) -> text "%vF_" <> pprUniqueAlways u
RegVirtual (VirtualRegD u) -> text "%vD_" <> pprUniqueAlways u
RegVirtual (VirtualRegV128 u) -> text "%vV128_" <> pprUniqueAlways u
=====================================
compiler/GHC/CmmToAsm/PPC/Regs.hs
=====================================
@@ -86,7 +86,7 @@ virtualRegSqueeze cls vr
RcFloatOrVector
-> case vr of
VirtualRegD{} -> 1
- VirtualRegF{} -> 0
+ VirtualRegV128{} -> 1
_other -> 0
{-# INLINE realRegSqueeze #-}
=====================================
compiler/GHC/CmmToAsm/Reg/Graph/TrivColorable.hs
=====================================
@@ -239,8 +239,8 @@ allocatableRegsInteger
= length $ filter (\r -> regClass r == RcInteger)
$ map RealReg allocatableRegs
-allocatableRegsFloat :: Int
-allocatableRegsFloat
- = length $ filter (\r -> regClass r == RcFloatOrVector
+allocatableRegsDouble :: Int
+allocatableRegsDouble
+ = length $ filter (\r -> regClass r == RcFloatOrVector)
$ map RealReg allocatableRegs
-}
=====================================
compiler/GHC/CmmToAsm/X86/CodeGen.hs
=====================================
@@ -1704,7 +1704,7 @@ getRegister' platform is32Bit (CmmMachOp mop [x, y]) = do -- dyadic MachOps
imm = litToImm lit
code dst
= case lit of
- CmmInt 0 _ -> exp `snocOL` (MOVSD FF32 (OpReg r) (OpReg dst))
+ CmmInt 0 _ -> exp `snocOL` (MOV FF32 (OpReg r) (OpReg dst))
CmmInt _ _ -> exp `snocOL` (VPSHUFD format imm (OpReg r) dst)
_ -> panic "Error in offset while unpacking"
return (Any format code)
@@ -1715,7 +1715,7 @@ getRegister' platform is32Bit (CmmMachOp mop [x, y]) = do -- dyadic MachOps
code dst
= case lit of
CmmInt 0 _ -> exp `snocOL`
- (MOVSD FF64 (OpReg r) (OpReg dst))
+ (MOV FF64 (OpReg r) (OpReg dst))
CmmInt 1 _ -> exp `snocOL`
(MOVHLPS format (OpReg r) dst)
_ -> panic "Error in offset while unpacking"
@@ -1901,11 +1901,11 @@ getRegister' platform _is32Bit (CmmMachOp mop [x, y, z]) = do -- ternary MachOps
= case offset of
CmmInt 0 _ -> valExp `appOL`
vecExp `snocOL`
- (MOVSD FF64 (OpReg valReg) (OpReg dst)) `snocOL`
+ (MOV FF64 (OpReg valReg) (OpReg dst)) `snocOL`
(SHUFPD fmt (ImmInt 0b00) (OpReg vecReg) dst)
CmmInt 1 _ -> valExp `appOL`
vecExp `snocOL`
- (MOVSD FF64 (OpReg vecReg) (OpReg dst)) `snocOL`
+ (MOV FF64 (OpReg vecReg) (OpReg dst)) `snocOL`
(SHUFPD fmt (ImmInt 0b00) (OpReg valReg) dst)
_ -> pprPanic "MO_VF_Insert DoubleX2: unsupported offset" (ppr offset)
in return $ Any fmt code
=====================================
compiler/GHC/CmmToAsm/X86/Instr.hs
=====================================
@@ -1,3 +1,4 @@
+{-# LANGUAGE LambdaCase #-}
{-# LANGUAGE TypeFamilies #-}
-----------------------------------------------------------------------------
@@ -373,7 +374,6 @@ data Instr
| MOVA Format Operand Operand
| MOVDQU Format Operand Operand
| VMOVDQU Format Operand Operand
- | MOVSD Format Operand Operand
-- logic operations
| VPXOR Format Reg Reg Reg
@@ -530,7 +530,6 @@ regUsageOfInstr platform instr
MOVH fmt src dst -> mkRU fmt (use_R src []) (use_R dst [])
MOVDQU fmt src dst -> mkRU fmt (use_R src []) (use_R dst [])
VMOVDQU fmt src dst -> mkRU fmt (use_R src []) (use_R dst [])
- MOVSD fmt src dst -> mkRU fmt (use_R src []) (use_R dst [])
VPXOR fmt s1 s2 dst -> mkRU fmt [s1,s2] [dst]
@@ -746,7 +745,6 @@ patchRegsOfInstr instr env
MOVH fmt src dst -> MOVH fmt (patchOp src) (patchOp dst)
MOVDQU fmt src dst -> MOVDQU fmt (patchOp src) (patchOp dst)
VMOVDQU fmt src dst -> VMOVDQU fmt (patchOp src) (patchOp dst)
- MOVSD fmt src dst -> MOVSD fmt (patchOp src) (patchOp dst)
VPXOR fmt s1 s2 dst -> VPXOR fmt (env s1) (env s2) (env dst)
@@ -968,9 +966,6 @@ mkRegRegMoveInstr _platform fmt@(VecFormat _ s) src dst
then MOVU fmt (OpReg src) (OpReg dst)
else VMOVU fmt (OpReg src) (OpReg dst)
mkRegRegMoveInstr _platform fmt src dst
- | isFloatFormat fmt
- = MOVSD fmt (OpReg src) (OpReg dst)
- | otherwise
= MOV fmt (OpReg src) (OpReg dst)
-- | Check whether an instruction represents a reg-reg move.
@@ -982,31 +977,32 @@ takeRegRegMoveInstr
-> Instr
-> Maybe (Reg,Reg)
-takeRegRegMoveInstr platform (MOV fmt (OpReg r1) (OpReg r2))
- -- MOV zeroes the upper part of vector registers,
- -- so it is not a real "move" in that case.
- | not (isVecFormat fmt)
- -- Don't eliminate a move between e.g. RAX and XMM:
- -- even though we might be using XMM to store a scalar integer value,
- -- some instructions only support XMM registers.
- , targetClassOfReg platform r1 == targetClassOfReg platform r2
- = Just (r1,r2)
-takeRegRegMoveInstr _ (MOVSD fmt (OpReg r1) (OpReg r2))
- | not (isVecFormat fmt)
- = Just (r1,r2)
-takeRegRegMoveInstr _ (MOVA _ (OpReg r1) (OpReg r2))
- = Just (r1, r2)
-takeRegRegMoveInstr _ (MOVU _ (OpReg r1) (OpReg r2))
- = Just (r1, r2)
-takeRegRegMoveInstr _ (VMOVU _ (OpReg r1) (OpReg r2))
- = Just (r1, r2)
-takeRegRegMoveInstr _ (MOVDQU _ (OpReg r1) (OpReg r2))
- = Just (r1, r2)
-takeRegRegMoveInstr _ (VMOVDQU _ (OpReg r1) (OpReg r2))
- = Just (r1, r2)
-
-takeRegRegMoveInstr _ _ = Nothing
-
+takeRegRegMoveInstr platform = \case
+ MOV fmt (OpReg r1) (OpReg r2)
+ -- MOV zeroes the upper part of vector registers,
+ -- so it is not a real "move" in that case.
+ | not (isVecFormat fmt)
+ -> go r1 r2
+ MOVA _ (OpReg r1) (OpReg r2)
+ -> go r1 r2
+ MOVU _ (OpReg r1) (OpReg r2)
+ -> go r1 r2
+ VMOVU _ (OpReg r1) (OpReg r2)
+ -> go r1 r2
+ MOVDQU _ (OpReg r1) (OpReg r2)
+ -> go r1 r2
+ VMOVDQU _ (OpReg r1) (OpReg r2)
+ -> go r1 r2
+ _ -> Nothing
+ where
+ go r1 r2
+ -- Don't eliminate a move between e.g. RAX and XMM:
+ -- even though we might be using XMM to store a scalar integer value,
+ -- some instructions only support XMM registers.
+ | targetClassOfReg platform r1 == targetClassOfReg platform r2
+ = Just (r1, r2)
+ | otherwise
+ = Nothing
-- | Make an unconditional branch instruction.
mkJumpInstr
=====================================
compiler/GHC/CmmToAsm/X86/Ppr.hs
=====================================
@@ -293,7 +293,6 @@ pprReg platform f r
else ppr64_reg_no f i
RegVirtual (VirtualRegI u) -> text "%vI_" <> pprUniqueAlways u
RegVirtual (VirtualRegHi u) -> text "%vHi_" <> pprUniqueAlways u
- RegVirtual (VirtualRegF u) -> text "%vF_" <> pprUniqueAlways u
RegVirtual (VirtualRegD u) -> text "%vD_" <> pprUniqueAlways u
RegVirtual (VirtualRegV128 u) -> text "%vVec_" <> pprUniqueAlways u
@@ -973,8 +972,6 @@ pprInstr platform i = case i of
-> pprOpOp (text "movdqu") format from to
VMOVDQU format from to
-> pprOpOp (text "vmovdqu") format from to
- MOVSD format from to
- -> pprOpOp (text "movsd") format from to
VPXOR format s1 s2 dst
-> pprXor (text "vpxor") format s1 s2 dst
=====================================
compiler/GHC/CmmToAsm/X86/Regs.hs
=====================================
@@ -80,8 +80,7 @@ virtualRegSqueeze cls vr
RcFloatOrVector
-> case vr of
VirtualRegD{} -> 1
- VirtualRegF{} -> 0
- VirtualRegV128{} -> 1
+ VirtualRegV128{} -> 1
_other -> 0
=====================================
compiler/GHC/Platform/Reg.hs
=====================================
@@ -60,8 +60,6 @@ data VirtualReg
= VirtualRegI { virtualRegUnique :: {-# UNPACK #-} !Unique }
-- | High part of 2-word virtual register
| VirtualRegHi { virtualRegUnique :: {-# UNPACK #-} !Unique }
- -- | Float virtual register
- | VirtualRegF { virtualRegUnique :: {-# UNPACK #-} !Unique }
-- | Double virtual register
| VirtualRegD { virtualRegUnique :: {-# UNPACK #-} !Unique }
-- | 128-bit wide vector virtual register
@@ -87,7 +85,6 @@ instance Outputable VirtualReg where
= case reg of
VirtualRegI u -> text "%vI_" <> pprUniqueAlways u
VirtualRegHi u -> text "%vHi_" <> pprUniqueAlways u
- VirtualRegF u -> text "%vFloat_" <> pprUniqueAlways u
VirtualRegD u -> text "%vDouble_" <> pprUniqueAlways u
VirtualRegV128 u -> text "%vV128_" <> pprUniqueAlways u
@@ -100,7 +97,6 @@ classOfVirtualReg vr
= case vr of
VirtualRegI{} -> RcInteger
VirtualRegHi{} -> RcInteger
- VirtualRegF{} -> RcFloatOrVector
VirtualRegD{} -> RcFloatOrVector
VirtualRegV128{} -> RcFloatOrVector
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/commit/9ffe722ed4bbbc77b9a4409dff8dcdc4822975ac
--
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/commit/9ffe722ed4bbbc77b9a4409dff8dcdc4822975ac
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