[Git][ghc/ghc][wip/ncg-simd] fix regUsageOfInstr INSERTPS
sheaf (@sheaf)
gitlab at gitlab.haskell.org
Wed Jun 12 13:14:50 UTC 2024
sheaf pushed to branch wip/ncg-simd at Glasgow Haskell Compiler / GHC
Commits:
fa5e2b59 by sheaf at 2024-06-12T15:14:54+02:00
fix regUsageOfInstr INSERTPS
- - - - -
3 changed files:
- compiler/GHC/CmmToAsm/X86/CodeGen.hs
- compiler/GHC/CmmToAsm/X86/Instr.hs
- compiler/GHC/CmmToAsm/X86/Ppr.hs
Changes:
=====================================
compiler/GHC/CmmToAsm/X86/CodeGen.hs
=====================================
@@ -1648,7 +1648,7 @@ getRegister' platform is32Bit (CmmMachOp mop [x, y]) = do -- dyadic MachOps
(insertps 48)
where
insertps off =
- INSERTPS f (OpImm $ litToImm $ CmmInt off W32) (OpAddr addr) dst
+ INSERTPS f (litToImm $ CmmInt off W32) (OpAddr addr) dst
in return $ Any f code
vector_float_broadcast_sse _ _ c _
@@ -1721,13 +1721,13 @@ getRegister' platform is32Bit (CmmMachOp mop [x, y]) = do -- dyadic MachOps
.|. shiftL dst 4
vec src = if src >= 4 then v2 else v1
in unitOL
- (INSERTPS fmt (OpImm $ ImmInt $ insertImm i1 0 .|. 0b1110) (OpReg $ vec i1) dst)
+ (INSERTPS fmt (ImmInt $ insertImm i1 0 .|. 0b1110) (OpReg $ vec i1) dst)
`snocOL`
- (INSERTPS fmt (OpImm $ ImmInt $ insertImm i2 1) (OpReg $ vec i2) dst)
+ (INSERTPS fmt (ImmInt $ insertImm i2 1) (OpReg $ vec i2) dst)
`snocOL`
- (INSERTPS fmt (OpImm $ ImmInt $ insertImm i3 2) (OpReg $ vec i3) dst)
+ (INSERTPS fmt (ImmInt $ insertImm i3 2) (OpReg $ vec i3) dst)
`snocOL`
- (INSERTPS fmt (OpImm $ ImmInt $ insertImm i4 3) (OpReg $ vec i4) dst)
+ (INSERTPS fmt (ImmInt $ insertImm i4 3) (OpReg $ vec i4) dst)
_ -> pprPanic "vector shuffle: wrong number of indices (expected 4)" (ppr is)
_ ->
pprPanic "vector shuffle: unsupported format" (ppr fmt)
@@ -1770,7 +1770,7 @@ getRegister' platform _is32Bit (CmmMachOp mop [x, y, z]) = do -- ternary MachOps
imm = litToImm offset
code dst = exp `appOL`
(fn dst) `snocOL`
- (INSERTPS fmt (OpImm imm) (OpReg r) dst)
+ (INSERTPS fmt imm (OpReg r) dst)
in return $ Any fmt code
-- DoubleX2
vector_float_insert len at 2 W64 vecExpr valExpr (CmmLit offset)
=====================================
compiler/GHC/CmmToAsm/X86/Instr.hs
=====================================
@@ -361,8 +361,8 @@ data Instr
-- NOTE: Instructions follow the AT&T syntax
-- Constructors and deconstructors
| VBROADCAST Format AddrMode Reg
- | VEXTRACT Format Operand Reg Operand
- | INSERTPS Format Operand Operand Reg
+ | VEXTRACT Format Imm Reg Operand
+ | INSERTPS Format Imm Operand Reg
-- move operations
| VMOVU Format Operand Operand
@@ -505,9 +505,18 @@ regUsageOfInstr platform instr
-- vector instructions
VBROADCAST fmt src dst -> mkRU fmt (use_EA src []) [dst]
- VEXTRACT fmt off src dst -> mkRU fmt ((use_R off []) ++ [src]) (use_R dst [])
- INSERTPS fmt off src dst
- -> mkRU fmt ((use_R off []) ++ (use_R src [])) [dst]
+ VEXTRACT fmt _off src dst -> mkRU fmt [src] (use_R dst [])
+ INSERTPS fmt (ImmInt off) src dst
+ -> mkRU fmt ((use_R src []) ++ [dst | not doesNotReadDst]) [dst]
+ where
+ -- Compute whether the instruction reads the destination register or not.
+ -- Immediate bits: ss_dd_zzzz s = src pos, d = dst pos, z = zeroed components.
+ doesNotReadDst = and [ testBit off i | i <- [0, 1, 2, 3], i /= pos ]
+ -- Check whether the positions in which we are not inserting
+ -- are being zeroed.
+ where pos = ( off `shiftR` 4 ) .&. 0b11
+ INSERTPS fmt _off src dst
+ -> mkRU fmt ((use_R src []) ++ [dst]) [dst]
VMOVU fmt src dst -> mkRU fmt (use_R src []) (use_R dst [])
MOVU fmt src dst -> mkRU fmt (use_R src []) (use_R dst [])
@@ -713,9 +722,9 @@ patchRegsOfInstr instr env
-- vector instructions
VBROADCAST fmt src dst -> VBROADCAST fmt (lookupAddr src) (env dst)
VEXTRACT fmt off src dst
- -> VEXTRACT fmt (patchOp off) (env src) (patchOp dst)
+ -> VEXTRACT fmt off (env src) (patchOp dst)
INSERTPS fmt off src dst
- -> INSERTPS fmt (patchOp off) (patchOp src) (env dst)
+ -> INSERTPS fmt off (patchOp src) (env dst)
VMOVU fmt src dst -> VMOVU fmt (patchOp src) (patchOp dst)
MOVU fmt src dst -> MOVU fmt (patchOp src) (patchOp dst)
=====================================
compiler/GHC/CmmToAsm/X86/Ppr.hs
=====================================
@@ -965,7 +965,7 @@ pprInstr platform i = case i of
VPXOR format s1 s2 dst
-> pprXor (text "vpxor") format s1 s2 dst
VEXTRACT format offset from to
- -> pprFormatOpRegOp (text "vextract") format offset from to
+ -> pprFormatImmRegOp (text "vextract") format offset from to
INSERTPS format offset addr dst
-> pprInsert (text "insertps") format offset addr dst
VPSHUFD format offset src dst
@@ -1098,11 +1098,11 @@ pprInstr platform i = case i of
pprOperand platform out_fmt op2
]
- pprFormatOpRegOp :: Line doc -> Format -> Operand -> Reg -> Operand -> doc
- pprFormatOpRegOp name format off reg1 op2
+ pprFormatImmRegOp :: Line doc -> Format -> Imm -> Reg -> Operand -> doc
+ pprFormatImmRegOp name format off reg1 op2
= line $ hcat [
pprMnemonic name format,
- pprOperand platform format off,
+ pprDollImm off,
comma,
pprReg platform format reg1,
comma,
@@ -1252,11 +1252,11 @@ pprInstr platform i = case i of
pprReg platform format reg3
]
- pprInsert :: Line doc -> Format -> Operand -> Operand -> Reg -> doc
+ pprInsert :: Line doc -> Format -> Imm -> Operand -> Reg -> doc
pprInsert name format off src dst
= line $ hcat [
pprGenMnemonic name format,
- pprOperand platform format off,
+ pprDollImm off,
comma,
pprOperand platform format src,
comma,
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/commit/fa5e2b59dd27f21470c3ca4053fc986fe6a670e9
--
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/commit/fa5e2b59dd27f21470c3ca4053fc986fe6a670e9
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