[Git][ghc/ghc][wip/tsan/fixes-2] 24 commits: cmm: Introduce MO_RelaxedRead
Ben Gamari (@bgamari)
gitlab at gitlab.haskell.org
Tue Jun 20 11:01:27 UTC 2023
Ben Gamari pushed to branch wip/tsan/fixes-2 at Glasgow Haskell Compiler / GHC
Commits:
b7c12615 by Ben Gamari at 2023-06-20T07:01:19-04:00
cmm: Introduce MO_RelaxedRead
In hand-written Cmm it can sometimes be necessary to atomically load
from memory deep within an expression (e.g. see the `CHECK_GC` macro).
This MachOp provides a convenient way to do so without breaking the
expression into multiple statements.
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3071e04c by Ben Gamari at 2023-06-20T07:01:19-04:00
rts: Silence spurious data races in ticky counters
Previously we would use non-atomic accesses when bumping ticky counters,
which would result in spurious data race reports from ThreadSanitizer
when the threaded RTS was in use.
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1e36ebbf by Ben Gamari at 2023-06-20T07:01:19-04:00
Improve TSAN documentation
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fbef2577 by Ben Gamari at 2023-06-20T07:01:19-04:00
rts: Fix data race in Interpreter's preemption check
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4e0e2a93 by Ben Gamari at 2023-06-20T07:01:19-04:00
rts: Fix data race in threadStatus#
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4089e22a by Ben Gamari at 2023-06-20T07:01:19-04:00
rts: Fix data race in CHECK_GC
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8cbfd523 by Ben Gamari at 2023-06-20T07:01:21-04:00
rts: Relaxed ticky
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2af80d3c by Ben Gamari at 2023-06-20T07:01:21-04:00
base: use atomic write when updating timer manager
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1001d7d3 by Ben Gamari at 2023-06-20T07:01:21-04:00
Use relaxed atomics to manipulate TSO status fields
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976a3a0f by Ben Gamari at 2023-06-20T07:01:21-04:00
rts: Add necessary barriers when manipulating TSO owner
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0697b162 by Ben Gamari at 2023-06-20T07:01:21-04:00
rts: Fix synchronization on thread blocking state
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bf91365b by Ben Gamari at 2023-06-20T07:01:21-04:00
rts: Relaxed load MutVar info table
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86b80408 by Ben Gamari at 2023-06-20T07:01:21-04:00
hadrian: More debug information
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625577fb by Ben Gamari at 2023-06-20T07:01:21-04:00
hadrian: More selective TSAN instrumentation
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a52f26f2 by Ben Gamari at 2023-06-20T07:01:21-04:00
codeGen/tsan: Rework handling of spilling
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1822973d by Ben Gamari at 2023-06-20T07:01:21-04:00
codeGen: Ensure that TSAN is aware of writeArray# write barriers
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6678e430 by Ben Gamari at 2023-06-20T07:01:21-04:00
codeGen: Ensure that array reads have necessary barriers
This was the cause of #23541.
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05a0ce5d by Ben Gamari at 2023-06-20T07:01:21-04:00
Wordsmith TSAN Note
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76989854 by Ben Gamari at 2023-06-20T07:01:21-04:00
codeGen: Use relaxed accesses in ticky bumping
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69af1402 by Ben Gamari at 2023-06-20T07:01:21-04:00
codeGen: Use relaxed-read in closureInfoPtr
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134526e4 by Ben Gamari at 2023-06-20T07:01:22-04:00
Fix thunk update ordering
Previously we attempted to ensure soundness of concurrent thunk update
by synchronizing on the access of the thunk's info table pointer field.
This was believed to be sufficient since the indirectee (which may
expose a closure allocated by another core) would not be examined
until the info table pointer update is complete.
However, it turns out that this can result in data races in the presence
of multiple threads racing a update a single thunk. For instance,
consider this interleaving under the old scheme:
Thread A Thread B
--------- ---------
t=0 Enter t
1 Push update frame
2 Begin evaluation
4 Pause thread
5 t.indirectee=tso
6 Release t.info=BLACKHOLE
7 ... (e.g. GC)
8 Resume thread
9 Finish evaluation
10 Relaxed t.indirectee=x
11 Load t.info
12 Acquire fence
13 Inspect t.indirectee
14 Release t.info=BLACKHOLE
Here Thread A enters thunk `t` but is soon paused, resulting in `t`
being lazily blackholed at t=6. Then, at t=10 Thread A finishes
evaluation and updates `t.indirectee` with a relaxed store.
Meanwhile, Thread B enters the blackhole. Under the old scheme this
would introduce an acquire-fence but this would only synchronize with
Thread A at t=6. Consequently, the result of the evaluation, `x`, is not
visible to Thread B, introducing a data race.
We fix this by treating the `indirectee` field as we do all other
mutable fields. This means we must always access this field with
acquire-loads and release-stores.
See #23185.
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011f88d2 by Ben Gamari at 2023-06-20T07:01:22-04:00
STM: Use acquire loads when possible
Full sequential consistency is not needed here.
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892ac9d9 by Ubuntu at 2023-06-20T07:01:22-04:00
ghc-prim: Use C11 atomics
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e5038a94 by Ubuntu at 2023-06-20T07:01:22-04:00
Run script
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30 changed files:
- compiler/GHC/Cmm/Expr.hs
- compiler/GHC/Cmm/Info.hs
- compiler/GHC/Cmm/MachOp.hs
- compiler/GHC/Cmm/Parser.y
- compiler/GHC/Cmm/ThreadSanitizer.hs
- compiler/GHC/CmmToAsm/AArch64/CodeGen.hs
- compiler/GHC/CmmToAsm/PPC/CodeGen.hs
- compiler/GHC/CmmToAsm/Wasm/FromCmm.hs
- compiler/GHC/CmmToAsm/X86/CodeGen.hs
- compiler/GHC/CmmToC.hs
- compiler/GHC/CmmToLlvm/CodeGen.hs
- compiler/GHC/StgToCmm/Bind.hs
- compiler/GHC/StgToCmm/Prim.hs
- compiler/GHC/StgToCmm/Ticky.hs
- compiler/GHC/StgToCmm/Utils.hs
- hadrian/src/Flavour.hs
- libraries/base/GHC/Event/Thread.hs
- libraries/ghc-prim/cbits/atomic.c
- rts/Apply.cmm
- rts/Compact.cmm
- rts/Exception.cmm
- rts/Heap.c
- rts/HeapStackCheck.cmm
- rts/Interpreter.c
- rts/Messages.c
- rts/PrimOps.cmm
- rts/RaiseAsync.c
- rts/STM.c
- rts/Schedule.c
- rts/StableName.c
The diff was not included because it is too large.
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/compare/c016e70ac9f39f669b59fe8f6fdaae7868d62fad...e5038a94be33dd96ef0040dde0585efcb6e0cdb4
--
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/compare/c016e70ac9f39f669b59fe8f6fdaae7868d62fad...e5038a94be33dd96ef0040dde0585efcb6e0cdb4
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