[Git][ghc/ghc][wip/tsan/fixes-2] 21 commits: cmm: Introduce MO_RelaxedRead

Ben Gamari (@bgamari) gitlab at gitlab.haskell.org
Tue Jun 20 03:34:31 UTC 2023



Ben Gamari pushed to branch wip/tsan/fixes-2 at Glasgow Haskell Compiler / GHC


Commits:
cc1b407b by Ben Gamari at 2023-06-19T22:50:14-04:00
cmm: Introduce MO_RelaxedRead

In hand-written Cmm it can sometimes be necessary to atomically load
from memory deep within an expression (e.g. see the `CHECK_GC` macro).
This MachOp provides a convenient way to do so without breaking the
expression into multiple statements.

- - - - -
a97eba78 by Ben Gamari at 2023-06-19T22:50:14-04:00
rts: Silence spurious data races in ticky counters

Previously we would use non-atomic accesses when bumping ticky counters,
which would result in spurious data race reports from ThreadSanitizer
when the threaded RTS was in use.

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f407fa90 by Ben Gamari at 2023-06-19T22:50:14-04:00
Improve TSAN documentation

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46d6d4e7 by Ben Gamari at 2023-06-19T22:50:14-04:00
rts: Fix various data races

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a1f593e0 by Ben Gamari at 2023-06-19T22:50:14-04:00
base: use atomic write when updating timer manager

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2d7123ae by Ben Gamari at 2023-06-19T22:50:14-04:00
Use relaxed atomics to manipulate TSO status fields

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9c936fff by Ben Gamari at 2023-06-19T22:50:14-04:00
rts: Add necessary barriers when manipulating TSO owner

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6d7d123a by Ben Gamari at 2023-06-19T22:50:14-04:00
rts: Fix synchronization on thread blocking state

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d02fe49c by Ben Gamari at 2023-06-19T22:50:14-04:00
rts: Relaxed load MutVar info table

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dadb3d2e by Ben Gamari at 2023-06-19T22:50:14-04:00
hadrian: More debug information

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7b33d535 by Ben Gamari at 2023-06-19T22:50:14-04:00
hadrian: More selective TSAN instrumentation

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ada5171f by Ben Gamari at 2023-06-19T22:50:14-04:00
codeGen/tsan: Rework handling of spilling

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4a9c2975 by Ben Gamari at 2023-06-19T22:50:15-04:00
codeGen: Ensure that TSAN is aware of writeArray# write barriers

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3dd52b2c by Ben Gamari at 2023-06-19T22:50:15-04:00
codeGen: Ensure that array reads have necessary barriers

This was the cause of #23541.

- - - - -
43c527f0 by Ben Gamari at 2023-06-19T22:50:15-04:00
Wordsmith TSAN Note

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a1632166 by Ben Gamari at 2023-06-19T22:50:15-04:00
codeGen: Use relaxed accesses in ticky bumping

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ee67cb5c by Ben Gamari at 2023-06-19T22:50:15-04:00
codeGen: Use relaxed-read in closureInfoPtr

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ea485334 by Ben Gamari at 2023-06-19T22:50:15-04:00
Fix thunk update ordering

Previously we attempted to ensure soundness of concurrent thunk update
by synchronizing on the access of the thunk's info table pointer field.
This was believed to be sufficient since the indirectee (which may
expose a closure allocated by another core) would not be examined
until the info table pointer update is complete.

However, it turns out that this can result in data races in the presence
of multiple threads racing a update a single thunk. For instance,
consider this interleaving under the old scheme:

            Thread A                             Thread B
            ---------                            ---------
    t=0     Enter t
      1     Push update frame
      2     Begin evaluation

      4     Pause thread
      5     t.indirectee=tso
      6     Release t.info=BLACKHOLE

      7     ... (e.g. GC)

      8     Resume thread
      9     Finish evaluation
      10    Relaxed t.indirectee=x

      11                                         Load t.info
      12                                         Acquire fence
      13                                         Inspect t.indirectee

      14    Release t.info=BLACKHOLE

Here Thread A enters thunk `t` but is soon paused, resulting in `t`
being lazily blackholed at t=6. Then, at t=10 Thread A finishes
evaluation and updates `t.indirectee` with a relaxed store.

Meanwhile, Thread B enters the blackhole. Under the old scheme this
would introduce an acquire-fence but this would only synchronize with
Thread A at t=6. Consequently, the result of the evaluation, `x`, is not
visible to Thread B, introducing a data race.

We fix this by treating the `indirectee` field as we do all other
mutable fields. This means we must always access this field with
acquire-loads and release-stores.

See #23185.

- - - - -
6591a664 by Ben Gamari at 2023-06-19T22:50:15-04:00
STM: Use acquire loads when possible

Full sequential consistency is not needed here.

- - - - -
7c82f5c9 by Ubuntu at 2023-06-19T22:50:15-04:00
ghc-prim: Use C11 atomics

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c016e70a by Ubuntu at 2023-06-19T22:50:15-04:00
Run script

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30 changed files:

- compiler/GHC/Cmm/Expr.hs
- compiler/GHC/Cmm/Info.hs
- compiler/GHC/Cmm/MachOp.hs
- compiler/GHC/Cmm/Parser.y
- compiler/GHC/Cmm/ThreadSanitizer.hs
- compiler/GHC/CmmToAsm/AArch64/CodeGen.hs
- compiler/GHC/CmmToAsm/PPC/CodeGen.hs
- compiler/GHC/CmmToAsm/Wasm/FromCmm.hs
- compiler/GHC/CmmToAsm/X86/CodeGen.hs
- compiler/GHC/CmmToC.hs
- compiler/GHC/CmmToLlvm/CodeGen.hs
- compiler/GHC/StgToCmm/Bind.hs
- compiler/GHC/StgToCmm/Prim.hs
- compiler/GHC/StgToCmm/Ticky.hs
- compiler/GHC/StgToCmm/Utils.hs
- hadrian/src/Flavour.hs
- libraries/base/GHC/Event/Thread.hs
- libraries/ghc-prim/cbits/atomic.c
- rts/Apply.cmm
- rts/Compact.cmm
- rts/Exception.cmm
- rts/Heap.c
- rts/HeapStackCheck.cmm
- rts/Interpreter.c
- rts/Messages.c
- rts/PrimOps.cmm
- rts/RaiseAsync.c
- rts/STM.c
- rts/Schedule.c
- rts/StableName.c


The diff was not included because it is too large.


View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/compare/ed7bf9c80fe2bc3415d79c8f168a65c177345a50...c016e70ac9f39f669b59fe8f6fdaae7868d62fad

-- 
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/compare/ed7bf9c80fe2bc3415d79c8f168a65c177345a50...c016e70ac9f39f669b59fe8f6fdaae7868d62fad
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