[Git][ghc/ghc][wip/supersven/riscv64-ncg] Implement MO_ReadBarrier and MO_WriteBarrier

[Sven Tennie (@supersven)]

Sven Tennie pushed to branch wip/supersven/riscv64-ncg at Glasgow Haskell Compiler / GHC


Commits:
0ca4e9c0 by Sven Tennie at 2023-06-10T16:43:51+00:00
Implement MO_ReadBarrier and MO_WriteBarrier

The levels are taken from SMP.h write_barrier() and load_load_barrier().

- - - - -


3 changed files:

- compiler/GHC/CmmToAsm/RV64/CodeGen.hs
- compiler/GHC/CmmToAsm/RV64/Instr.hs
- compiler/GHC/CmmToAsm/RV64/Ppr.hs


Changes:

=====================================
compiler/GHC/CmmToAsm/RV64/CodeGen.hs
=====================================
@@ -1576,9 +1576,9 @@ genCCall target dest_regs arg_regs bid = do
         MO_U_Mul2     _w -> unsupported mop
 
         -- Memory Ordering
-        -- TODO DMBSY is probably *way* too much!
-        MO_ReadBarrier      ->  return (unitOL DMBSY, Nothing)
-        MO_WriteBarrier     ->  return (unitOL DMBSY, Nothing)
+        -- The concrete encoding is copied from load_load_barrier() and write_barrier() (SMP.h)
+        MO_ReadBarrier      ->  return (unitOL (DMBSY DmbRead), Nothing)
+        MO_WriteBarrier     ->  return (unitOL (DMBSY DmbWrite), Nothing)
         MO_Touch            ->  return (nilOL, Nothing) -- Keep variables live (when using interior pointers)
         -- Prefetch
         MO_Prefetch_Data _n -> return (nilOL, Nothing) -- Prefetch hint.


=====================================
compiler/GHC/CmmToAsm/RV64/Instr.hs
=====================================
@@ -132,7 +132,7 @@ regUsageOfInstr platform instr = case instr of
   -- LDP _ dst1 dst2 src      -> usage (regOp src, regOp dst1 ++ regOp dst2)
 
   -- 8. Synchronization Instructions -------------------------------------------
-  DMBSY                    -> usage ([], [])
+  DMBSY _                  -> usage ([], [])
 
   -- 9. Floating Point Instructions --------------------------------------------
   FCVT dst src             -> usage (regOp src, regOp dst)
@@ -268,7 +268,7 @@ patchRegsOfInstr instr env = case instr of
     -- LDP f o1 o2 o3 -> LDP f (patchOp o1) (patchOp o2) (patchOp o3)
 
     -- 8. Synchronization Instructions -----------------------------------------
-    DMBSY          -> DMBSY
+    DMBSY op         -> DMBSY op
 
     -- 9. Floating Point Instructions ------------------------------------------
     FCVT o1 o2     -> FCVT (patchOp o1) (patchOp o2)
@@ -654,7 +654,7 @@ data Instr
     | BCOND Cond Operand Operand Target   -- branch with condition. b.<cond>
 
     -- 8. Synchronization Instructions -----------------------------------------
-    | DMBSY
+    | DMBSY DmbType
     -- 9. Floating Point Instructions
     -- Float ConVerT
     | FCVT Operand Operand
@@ -665,6 +665,8 @@ data Instr
     -- Float ABSolute value
     | FABS Operand Operand
 
+data DmbType = DmbRead | DmbWrite
+
 instrCon :: Instr -> String
 instrCon i =
     case i of


=====================================
compiler/GHC/CmmToAsm/RV64/Ppr.hs
=====================================
@@ -649,7 +649,9 @@ pprInstr platform instr = case instr of
   -- LDP _f o1 o2 o3 -> op3 (text "\tldp") o1 o2 o3
 
   -- 8. Synchronization Instructions -------------------------------------------
-  DMBSY -> line $ text "\tdmb sy"
+  DMBSY DmbRead -> line $ text "\tfence r,r"
+  DMBSY DmbWrite -> line $ text "\tfence w,w"
+
   -- 9. Floating Point Instructions --------------------------------------------
   FCVT o1 o2 -> op2 (text "\tfcvt") o1 o2
   SCVTF o1 o2 -> op2 (text "\tscvtf") o1 o2



View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/commit/0ca4e9c0e0b12a249671c7159e173a881c71581b

-- 
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/commit/0ca4e9c0e0b12a249671c7159e173a881c71581b
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