[Git][ghc/ghc][wip/tsan/fix-races] 22 commits: rts: Fix data race in threadPaused
Ben Gamari (@bgamari)
gitlab at gitlab.haskell.org
Mon Jul 24 18:39:43 UTC 2023
Ben Gamari pushed to branch wip/tsan/fix-races at Glasgow Haskell Compiler / GHC
Commits:
646d977d by Ben Gamari at 2023-07-24T14:39:27-04:00
rts: Fix data race in threadPaused
This only affects an assertion in the debug RTS and only needs relaxed
ordering.
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14f4534f by Ben Gamari at 2023-07-24T14:39:36-04:00
cmm: Introduce MO_RelaxedRead
In hand-written Cmm it can sometimes be necessary to atomically load
from memory deep within an expression (e.g. see the `CHECK_GC` macro).
This MachOp provides a convenient way to do so without breaking the
expression into multiple statements.
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3c48cd4e by Ben Gamari at 2023-07-24T14:39:36-04:00
rts: Silence spurious data races in ticky counters
Previously we would use non-atomic accesses when bumping ticky counters,
which would result in spurious data race reports from ThreadSanitizer
when the threaded RTS was in use.
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1b0f7d64 by Ben Gamari at 2023-07-24T14:39:36-04:00
codeGen: Use relaxed accesses in ticky bumping
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23422ad4 by Ben Gamari at 2023-07-24T14:39:36-04:00
rts: Fix data race in Interpreter's preemption check
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7feebec0 by Ben Gamari at 2023-07-24T14:39:36-04:00
rts: Fix data race in threadStatus#
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5def4d18 by Ben Gamari at 2023-07-24T14:39:36-04:00
rts: Fix data race in CHECK_GC
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87252027 by Ben Gamari at 2023-07-24T14:39:36-04:00
base: use atomic write when updating timer manager
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54ff735f by Ben Gamari at 2023-07-24T14:39:36-04:00
Use relaxed atomics to manipulate TSO status fields
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27341960 by Ben Gamari at 2023-07-24T14:39:36-04:00
rts: Add necessary barriers when manipulating TSO owner
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2f964518 by Ben Gamari at 2023-07-24T14:39:36-04:00
rts: Fix synchronization on thread blocking state
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0181a367 by Ben Gamari at 2023-07-24T14:39:36-04:00
rts: Use relaxed ordering on dirty/clean info tables updates
When changing the dirty/clean state of a mutable object we needn't have
any particular ordering.
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ee8b99b1 by Ben Gamari at 2023-07-24T14:39:36-04:00
Wordsmith TSAN Note
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dd426c0e by Ben Gamari at 2023-07-24T14:39:36-04:00
codeGen: Use relaxed-read in closureInfoPtr
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17ad4ce4 by Ben Gamari at 2023-07-24T14:39:36-04:00
Fix thunk update ordering
Previously we attempted to ensure soundness of concurrent thunk update
by synchronizing on the access of the thunk's info table pointer field.
This was believed to be sufficient since the indirectee (which may
expose a closure allocated by another core) would not be examined
until the info table pointer update is complete.
However, it turns out that this can result in data races in the presence
of multiple threads racing a update a single thunk. For instance,
consider this interleaving under the old scheme:
Thread A Thread B
--------- ---------
t=0 Enter t
1 Push update frame
2 Begin evaluation
4 Pause thread
5 t.indirectee=tso
6 Release t.info=BLACKHOLE
7 ... (e.g. GC)
8 Resume thread
9 Finish evaluation
10 Relaxed t.indirectee=x
11 Load t.info
12 Acquire fence
13 Inspect t.indirectee
14 Release t.info=BLACKHOLE
Here Thread A enters thunk `t` but is soon paused, resulting in `t`
being lazily blackholed at t=6. Then, at t=10 Thread A finishes
evaluation and updates `t.indirectee` with a relaxed store.
Meanwhile, Thread B enters the blackhole. Under the old scheme this
would introduce an acquire-fence but this would only synchronize with
Thread A at t=6. Consequently, the result of the evaluation, `x`, is not
visible to Thread B, introducing a data race.
We fix this by treating the `indirectee` field as we do all other
mutable fields. This means we must always access this field with
acquire-loads and release-stores.
See #23185.
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6d68c280 by Ben Gamari at 2023-07-24T14:39:36-04:00
STM: Use acquire loads when possible
Full sequential consistency is not needed here.
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22b33959 by Ben Gamari at 2023-07-24T14:39:37-04:00
rts/Interpreter: Fix data race
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2ae773fa by Ben Gamari at 2023-07-24T14:39:37-04:00
rts/Messages: Fix data race
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f404338a by Ben Gamari at 2023-07-24T14:39:37-04:00
rts/Prof: Fix data race
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807d24f6 by Ben Gamari at 2023-07-24T14:39:37-04:00
rts: Use fence rather than redundant load
Previously we would use an atomic load to ensure acquire ordering.
However, we now have `ACQUIRE_FENCE_ON`, which allows us to express this
more directly.
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42059a81 by Ben Gamari at 2023-07-24T14:39:37-04:00
rts: Fixes profiling timer races
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690a4e4f by Ben Gamari at 2023-07-24T14:39:37-04:00
rts/RaiseAsync: Drop redundant release fence
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30 changed files:
- compiler/GHC/Cmm/Expr.hs
- compiler/GHC/Cmm/Info.hs
- compiler/GHC/Cmm/MachOp.hs
- compiler/GHC/Cmm/Parser.y
- compiler/GHC/Cmm/ThreadSanitizer.hs
- compiler/GHC/CmmToAsm/AArch64/CodeGen.hs
- compiler/GHC/CmmToAsm/PPC/CodeGen.hs
- compiler/GHC/CmmToAsm/Wasm/FromCmm.hs
- compiler/GHC/CmmToAsm/X86/CodeGen.hs
- compiler/GHC/CmmToC.hs
- compiler/GHC/CmmToLlvm/CodeGen.hs
- compiler/GHC/StgToCmm/Bind.hs
- compiler/GHC/StgToCmm/Ticky.hs
- compiler/GHC/StgToCmm/Utils.hs
- libraries/base/GHC/Event/Thread.hs
- rts/Apply.cmm
- rts/Compact.cmm
- rts/Exception.cmm
- rts/Heap.c
- rts/HeapStackCheck.cmm
- rts/Interpreter.c
- rts/Messages.c
- rts/PrimOps.cmm
- rts/Proftimer.c
- rts/RaiseAsync.c
- rts/STM.c
- rts/Schedule.c
- rts/StableName.c
- rts/StgMiscClosures.cmm
- rts/StgStartup.cmm
The diff was not included because it is too large.
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/compare/b778e09017b1ce08b93a426fa194b2252e730d8b...690a4e4fac47008933e58836b6f3d28d772d7d68
--
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/compare/b778e09017b1ce08b93a426fa194b2252e730d8b...690a4e4fac47008933e58836b6f3d28d772d7d68
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