[Git][ghc/ghc][wip/andreask/arm_immediates] wip - add mov-imm use, remove comment
Andreas Klebinger (@AndreasK)
gitlab at gitlab.haskell.org
Tue Jul 18 14:02:56 UTC 2023
Andreas Klebinger pushed to branch wip/andreask/arm_immediates at Glasgow Haskell Compiler / GHC
Commits:
34a57e86 by Andreas Klebinger at 2023-07-18T16:05:06+02:00
wip - add mov-imm use, remove comment
- - - - -
2 changed files:
- compiler/GHC/CmmToAsm/AArch64/CodeGen.hs
- compiler/GHC/CmmToAsm/X86/Regs.hs
Changes:
=====================================
compiler/GHC/CmmToAsm/AArch64/CodeGen.hs
=====================================
@@ -580,8 +580,13 @@ getRegister' config plat expr
-- Those need the upper bits set. We'd either have to explicitly sign
-- or figure out something smarter. Lowered to
-- `MOV dst XZR`
+ CmmInt i w | i >= 0
+ , Just imm_op <- getMovWideImm i -> do
+ return (Any (intFormat w) (\dst -> unitOL $ annExpr expr (MOV (OpReg w dst) imm_op)))
+
CmmInt i w | isNbitEncodeable 16 i, i >= 0 -> do
return (Any (intFormat w) (\dst -> unitOL $ annExpr expr (MOV (OpReg W16 dst) (OpImm (ImmInteger i)))))
+
CmmInt i w | isNbitEncodeable 32 i, i >= 0 -> do
let half0 = fromIntegral (fromIntegral i :: Word16)
half1 = fromIntegral (fromIntegral (i `shiftR` 16) :: Word16)
=====================================
compiler/GHC/CmmToAsm/X86/Regs.hs
=====================================
@@ -275,11 +275,6 @@ The fp registers are all Double registers; we don't have any RcFloat class
regs. @regClass@ barfs if you give it a VirtualRegF, and mkVReg above should
never generate them.
-esp, esi, edi and ebp are reserved for specific purporses o *generally* free to use because they are
-reserved for reserved for
-
-eax ebx ecx edx
-
TODO: cleanup modelling float vs double registers and how they are the same class.
-}
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/commit/34a57e8600c54be93c9c2e6b7b0bfaeb5ba2dfc5
--
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/commit/34a57e8600c54be93c9c2e6b7b0bfaeb5ba2dfc5
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