[Git][ghc/ghc][wip/9.4.6-backports] Arm: Fix lack of zero-extension for 8/16 bit add/sub with immediate.

[Zubin (@wz1000)]

Zubin pushed to branch wip/9.4.6-backports at Glasgow Haskell Compiler / GHC


Commits:
30fed8fa by Andreas Klebinger at 2023-08-04T16:11:26+05:30
Arm: Fix lack of zero-extension for 8/16 bit add/sub with immediate.

For 32/64bit we can avoid explicit extension/zeroing as the instructions
set the full width of the registers.

When doing 16/8bit computation we have to put a bit more work in so we
can't use the fast path.

Fixes #23749 for 9.4.

(cherry picked from commit 0bb44f695bd008f03644e3d306566c50c5bd528c)

- - - - -


1 changed file:

- compiler/GHC/CmmToAsm/AArch64/CodeGen.hs


Changes:

=====================================
compiler/GHC/CmmToAsm/AArch64/CodeGen.hs
=====================================
@@ -693,12 +693,16 @@ getRegister' config plat expr
     -- 1. Compute Reg +/- n directly.
     --    For Add/Sub we can directly encode 12bits, or 12bits lsl #12.
     CmmMachOp (MO_Add w) [(CmmReg reg), CmmLit (CmmInt n _)]
-      | n > 0 && n < 4096 -> return $ Any (intFormat w) (\d -> unitOL $ annExpr expr (ADD (OpReg w d) (OpReg w' r') (OpImm (ImmInteger n))))
+      | n > 0 && n < 4096
+      , w == W32 || w == W64 -- Work around #23749
+      -> return $ Any (intFormat w) (\d -> unitOL $ annExpr expr (ADD (OpReg w d) (OpReg w' r') (OpImm (ImmInteger n))))
       -- TODO: 12bits lsl #12; e.g. lower 12 bits of n are 0; shift n >> 12, and set lsl to #12.
       where w' = formatToWidth (cmmTypeFormat (cmmRegType plat reg))
             r' = getRegisterReg plat reg
     CmmMachOp (MO_Sub w) [(CmmReg reg), CmmLit (CmmInt n _)]
-      | n > 0 && n < 4096 -> return $ Any (intFormat w) (\d -> unitOL $ annExpr expr (SUB (OpReg w d) (OpReg w' r') (OpImm (ImmInteger n))))
+      | n > 0 && n < 4096
+      , w == W32 || w == W64 -- Work around #23749
+      -> return $ Any (intFormat w) (\d -> unitOL $ annExpr expr (SUB (OpReg w d) (OpReg w' r') (OpImm (ImmInteger n))))
       -- TODO: 12bits lsl #12; e.g. lower 12 bits of n are 0; shift n >> 12, and set lsl to #12.
       where w' = formatToWidth (cmmTypeFormat (cmmRegType plat reg))
             r' = getRegisterReg plat reg



View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/commit/30fed8fabdd2833c754834e3b4131f2277dcc650

-- 
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/commit/30fed8fabdd2833c754834e3b4131f2277dcc650
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