[Git][ghc/ghc][wip/supersven/riscv64-ncg] Unsigned remainder (modulo): REMU

[Sven Tennie (@supersven)]

Sven Tennie pushed to branch wip/supersven/riscv64-ncg at Glasgow Haskell Compiler / GHC


Commits:
c8fd8d51 by Sven Tennie at 2023-08-01T10:16:13+02:00
Unsigned remainder (modulo): REMU

- - - - -


3 changed files:

- compiler/GHC/CmmToAsm/RV64/CodeGen.hs
- compiler/GHC/CmmToAsm/RV64/Instr.hs
- compiler/GHC/CmmToAsm/RV64/Ppr.hs


Changes:

=====================================
compiler/GHC/CmmToAsm/RV64/CodeGen.hs
=====================================
@@ -888,12 +888,11 @@ getRegister' config plat expr =
         MO_S_MulMayOflo w -> do_mul_may_oflo w x y
         MO_S_Quot w       -> intOp True w (\d x y -> unitOL $ annExpr expr (DIV d x y))
 
-        -- Note the swap in Rx and Ry.
         MO_S_Rem w -> intOp True w (\d x y -> unitOL $ annExpr expr (REM d x y))
 
         -- Unsigned multiply/divide
         MO_U_Quot w -> intOp False w (\d x y -> unitOL $ annExpr expr (DIVU d x y))
-        MO_U_Rem w  -> intOp False w (\d x y -> unitOL $ annExpr expr (REM d x y))
+        MO_U_Rem w  -> intOp False w (\d x y -> unitOL $ annExpr expr (REMU d x y))
 
         -- Signed comparisons -- see Note [CSET)
         MO_S_Ge w     -> intOp True  w (\d x y -> unitOL $ annExpr expr (CSET d x y SGE))


=====================================
compiler/GHC/CmmToAsm/RV64/Instr.hs
=====================================
@@ -88,6 +88,7 @@ regUsageOfInstr platform instr = case instr of
   SMULL dst src1 src2      -> usage (regOp src1 ++ regOp src2, regOp dst)
   DIV dst src1 src2        -> usage (regOp src1 ++ regOp src2, regOp dst)
   REM dst src1 src2        -> usage (regOp src1 ++ regOp src2, regOp dst)
+  REMU dst src1 src2       -> usage (regOp src1 ++ regOp src2, regOp dst)
   SUB dst src1 src2        -> usage (regOp src1 ++ regOp src2, regOp dst)
   DIVU dst src1 src2       -> usage (regOp src1 ++ regOp src2, regOp dst)
 
@@ -223,6 +224,7 @@ patchRegsOfInstr instr env = case instr of
     SMULL o1 o2 o3 -> SMULL (patchOp o1) (patchOp o2)  (patchOp o3)
     DIV o1 o2 o3   -> DIV (patchOp o1) (patchOp o2) (patchOp o3)
     REM o1 o2 o3   -> REM (patchOp o1) (patchOp o2) (patchOp o3)
+    REMU o1 o2 o3  -> REMU (patchOp o1) (patchOp o2) (patchOp o3)
     SUB o1 o2 o3   -> SUB  (patchOp o1) (patchOp o2) (patchOp o3)
     DIVU o1 o2 o3  -> DIVU (patchOp o1) (patchOp o2) (patchOp o3)
 
@@ -601,7 +603,8 @@ data Instr
     | NEG Operand Operand -- rd = -op2
 
     | DIV Operand Operand Operand -- rd = rn ÷ rm
-    | REM Operand Operand Operand -- rd = rn % rm
+    | REM Operand Operand Operand -- rd = rn % rm (signed)
+    | REMU Operand Operand Operand -- rd = rn % rm (unsigned)
 
     -- TODO: Rename: MULH
     | SMULH Operand Operand Operand
@@ -688,6 +691,7 @@ instrCon i =
       NEG{} -> "NEG"
       DIV{} -> "DIV"
       REM{} -> "REM"
+      REMU{} -> "REMU"
       SMULH{} -> "SMULH"
       SMULL{} -> "SMULL"
       SUB{} -> "SUB"


=====================================
compiler/GHC/CmmToAsm/RV64/Ppr.hs
=====================================
@@ -489,6 +489,7 @@ pprInstr platform instr = case instr of
   REM o1 o2 o3 | isFloatOp o1 && isFloatOp o2 && isFloatOp o3
     -> panic $ "pprInstr - REM not implemented for floats (yet)"
   REM o1 o2 o3 -> op3 (text "\trem") o1 o2 o3
+  REMU o1 o2 o3 -> op3 (text "\tremu") o1 o2 o3
 
   SUB  o1 o2 o3
     | isFloatOp o1 && isFloatOp o2 && isFloatOp o3 -> op3 (text "\tfsub." <> if isSingleOp o1 then text "s" else text "d") o1 o2 o3



View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/commit/c8fd8d51bf1cf5bce0cbc553c8aa8f13a23e185d

-- 
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/commit/c8fd8d51bf1cf5bce0cbc553c8aa8f13a23e185d
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