[Git][ghc/ghc][wip/angerman/aarch64-ncg] Revert the Spill/Reload fix; undo :got: loads.
Moritz Angermann
gitlab at gitlab.haskell.org
Tue Aug 18 02:29:26 UTC 2020
Moritz Angermann pushed to branch wip/angerman/aarch64-ncg at Glasgow Haskell Compiler / GHC
Commits:
cf52b0a1 by Moritz Angermann at 2020-08-18T02:29:12+00:00
Revert the Spill/Reload fix; undo :got: loads.
This breaks dynamic, however we can build a working
stage2 compiler with the following mk/build.mk
BuildFlavour = quick
ifneq "$(BuildFlavour)" ""
include mk/flavours/$(BuildFlavour).mk
endif
STRIP_CMD = :
DYNAMIC_BY_DEFAULT = NO
DYNAMIC_GHC_PROGRAMS = NO
- - - - -
10 changed files:
- compiler/GHC/CmmToAsm/AArch64/Instr.hs
- compiler/GHC/CmmToAsm/AArch64/Ppr.hs
- compiler/GHC/CmmToAsm/Instr.hs
- compiler/GHC/CmmToAsm/PPC/Instr.hs
- compiler/GHC/CmmToAsm/Reg/Linear.hs
- compiler/GHC/CmmToAsm/Reg/Linear/JoinToTargets.hs
- compiler/GHC/CmmToAsm/Reg/Linear/State.hs
- compiler/GHC/CmmToAsm/Reg/Liveness.hs
- compiler/GHC/CmmToAsm/SPARC/Instr.hs
- compiler/GHC/CmmToAsm/X86/Instr.hs
Changes:
=====================================
compiler/GHC/CmmToAsm/AArch64/Instr.hs
=====================================
@@ -1,5 +1,4 @@
-
-{-# language CPP #-}
+{-# language CPP, BangPatterns #-}
module GHC.CmmToAsm.AArch64.Instr
@@ -342,28 +341,47 @@ aarch64_mkSpillInstr
-> Reg -- register to spill
-> Int -- current stack delta
-> Int -- spill slot to use
- -> (Int, [Instr])
+ -> Instr
-- XXX this is stupid. We essentially do sp <- sp - 4095; str xN, [sp - ...] ; sp <- sp + 4095
+{-
aarch64_mkSpillInstr config reg delta slot | (spillSlotToOffset config slot) - delta > 4095
- = let (d, isns) = aarch64_mkSpillInstr config reg (delta + 4095) slot
- in (d, SUB sp sp (OpImm (ImmInt 4095)) : isns ++ [ADD sp sp (OpImm (ImmInt 4095))])
+ = let (!d, !isns) = traceShow msg $ aarch64_mkSpillInstr config reg (delta + delta') slot
+ in traceShow "Spill(1) ret" (d, subIsn : isns ++ [addIsn])
+ where delta' = 4095
+ !addIsn = ADD sp sp (OpImm (ImmInt delta'))
+ !subIsn = SUB sp sp (OpImm (ImmInt delta'))
+ msg = "Spill(1): " ++ show (spillSlotToOffset config slot) ++ "; Delta: " ++ show delta ++ " -> " ++ show (delta + delta')
aarch64_mkSpillInstr config reg delta slot | (spillSlotToOffset config slot) - delta > 255
- = let (d, isns) = aarch64_mkSpillInstr config reg (delta + delta') slot
- in (d, SUB sp sp (OpImm (ImmInt delta')) : isns ++ [ADD sp sp (OpImm (ImmInt delta'))])
+ = let (!d, !isns) = traceShow msg $ aarch64_mkSpillInstr config reg (delta + delta') slot
+ in traceShow "Spill(2) ret" (d, subIsn : isns ++ [addIsn])
where delta' = (spillSlotToOffset config slot) - delta
+ !addIsn = ADD sp sp (OpImm (ImmInt delta'))
+ !subIsn = SUB sp sp (OpImm (ImmInt delta'))
+ msg = "Spill(2): " ++ show (spillSlotToOffset config slot) ++ "; Delta: " ++ show delta ++ " -> " ++ show (delta + delta')
aarch64_mkSpillInstr config reg delta slot | (spillSlotToOffset config slot) - delta < -4095
- = let (d, isns) = aarch64_mkSpillInstr config reg (delta - 4095) slot
- in (d, ADD sp sp (OpImm (ImmInt 4095)) : isns ++ [SUB sp sp (OpImm (ImmInt 4095))])
+ = let (!d, !isns) = traceShow msg $ aarch64_mkSpillInstr config reg (delta - delta') slot
+ in traceShow "Spill(3) ret" (d, addIsn : isns ++ [subIsn])
+ where delta' = 4095
+ !addIsn = ADD sp sp (OpImm (ImmInt delta'))
+ !subIsn = SUB sp sp (OpImm (ImmInt delta'))
+ msg = "Spill(3): " ++ show (spillSlotToOffset config slot) ++ "; Delta: " ++ show delta ++ " -> " ++ show (delta + delta')
aarch64_mkSpillInstr config reg delta slot | (spillSlotToOffset config slot) - delta < -256
- = let (d, isns) = aarch64_mkSpillInstr config reg (delta + delta') slot
- in (d, SUB sp sp (OpImm (ImmInt delta')) : isns ++ [ADD sp sp (OpImm (ImmInt delta'))])
+ = let (!d, !isns) = traceShow msg $ aarch64_mkSpillInstr config reg (delta + delta') slot
+ in traceShow "Spill(4) ret" (d, subIsn : isns ++ [addIsn])
where delta' = (spillSlotToOffset config slot) - delta
-
+ !addIsn = ADD sp sp (OpImm (ImmInt delta'))
+ !subIsn = SUB sp sp (OpImm (ImmInt delta'))
+ msg = "Spill(4): " ++ show (spillSlotToOffset config slot) ++ "; Delta: " ++ show delta ++ " -> " ++ show (delta + delta')
+-}
aarch64_mkSpillInstr config reg delta slot
- = (delta, [ANN (text "Spill") $ STR fmt (OpReg W64 reg) (OpAddr (AddrRegImm (regSingle 31) (ImmInt $ off - delta)))])
+ = --[
+ -- ANN (text "Spill") $
+ -- traceShow ("Spill: " ++ show (off - delta)) $
+ STR fmt (OpReg W64 reg) (OpAddr (AddrRegImm (regSingle 31) (ImmInt $ off - delta)))
+ --]
where
fmt = case reg of
RegReal (RealRegSingle n) | n < 32 -> II64
@@ -375,29 +393,40 @@ aarch64_mkLoadInstr
-> Reg -- register to load
-> Int -- current stack delta
-> Int -- spill slot to use
- -> (Int, [Instr])
+ -> Instr
-- XXX this is stupid. We essentially do sp <- sp - 4095; str xN, [sp - ...] ; sp <- sp + 4095
+{-
aarch64_mkLoadInstr config reg delta slot | (spillSlotToOffset config slot) - delta > 4095
- = let (d, isns) = aarch64_mkLoadInstr config reg (delta + 4095) slot
- in (d, SUB sp sp (OpImm (ImmInt 4095)) : isns ++ [ADD sp sp (OpImm (ImmInt 4095))])
+ = let (!d, !isns) = traceShow msg $ aarch64_mkLoadInstr config reg (delta + delta') slot
+ in traceShow "Reload(1) ret" (d, SUB sp sp (OpImm (ImmInt 4095)) : isns ++ [ADD sp sp (OpImm (ImmInt 4095))])
+ where delta' = 4095
+ msg = "Reload(1): " ++ show (spillSlotToOffset config slot) ++ "; Delta: " ++ show delta ++ " -> " ++ show (delta + delta')
aarch64_mkLoadInstr config reg delta slot | (spillSlotToOffset config slot) - delta > 255
- = let (d, isns) = aarch64_mkLoadInstr config reg (delta + delta') slot
- in (d, SUB sp sp (OpImm (ImmInt delta')) : isns ++ [ADD sp sp (OpImm (ImmInt delta'))])
+ = let (!d, !isns) = traceShow msg $ aarch64_mkLoadInstr config reg (delta + delta') slot
+ in traceShow "Reload(2) ret" (d, SUB sp sp (OpImm (ImmInt delta')) : isns ++ [ADD sp sp (OpImm (ImmInt delta'))])
where delta' = (spillSlotToOffset config slot) - delta
+ msg = "Reload(2): " ++ show (spillSlotToOffset config slot) ++ "; Delta: " ++ show delta ++ " -> " ++ show (delta + delta')
aarch64_mkLoadInstr config reg delta slot | (spillSlotToOffset config slot) - delta < -4095
- = let (d, isns) = aarch64_mkLoadInstr config reg (delta - 4095) slot
- in (d, ADD sp sp (OpImm (ImmInt 4095)) : isns ++ [SUB sp sp (OpImm (ImmInt 4095))])
+ = let (!d, !isns) = traceShow msg $ aarch64_mkLoadInstr config reg (delta + delta') slot
+ in traceShow "Reload(3) ret" (d, ADD sp sp (OpImm (ImmInt 4095)) : isns ++ [SUB sp sp (OpImm (ImmInt 4095))])
+ where delta' = -4095
+ msg = "Reload(3): " ++ show (spillSlotToOffset config slot) ++ "; Delta: " ++ show delta ++ " -> " ++ show (delta + delta')
aarch64_mkLoadInstr config reg delta slot | (spillSlotToOffset config slot) - delta < -256
- = let (d, isns) = aarch64_mkLoadInstr config reg (delta + delta') slot
- in (d, SUB sp sp (OpImm (ImmInt delta')) : isns ++ [ADD sp sp (OpImm (ImmInt delta'))])
+ = let (!d, !isns) = traceShow msg $ aarch64_mkLoadInstr config reg (delta + delta') slot
+ in traceShow "Reload(4) ret" (d, SUB sp sp (OpImm (ImmInt delta')) : isns ++ [ADD sp sp (OpImm (ImmInt delta'))])
where delta' = (spillSlotToOffset config slot) - delta
+ msg = "Reload(4): " ++ show (spillSlotToOffset config slot) ++ "; Delta: " ++ show delta ++ " -> " ++ show (delta + delta')
-
+-}
aarch64_mkLoadInstr config reg delta slot
- = (delta, [ANN (text "Reload") $ LDR fmt (OpReg W64 reg) (OpAddr (AddrRegImm (regSingle 31) (ImmInt $ off - delta)))])
+ = --[
+ -- ANN (text "Reload") $
+ -- traceShow ("Reload: " ++ show (off - delta)) $
+ LDR fmt (OpReg W64 reg) (OpAddr (AddrRegImm (regSingle 31) (ImmInt $ off - delta)))
+ -- ]
where
fmt = case reg of
RegReal (RealRegSingle n) | n < 32 -> II64
=====================================
compiler/GHC/CmmToAsm/AArch64/Ppr.hs
=====================================
@@ -449,9 +449,9 @@ pprInstr platform instr = case instr of
-- 4. Branch Instructions ----------------------------------------------------
J t -> pprInstr platform (B t)
- B (TBlock bid) -> text "\tb" <+> ppr (mkLocalBlockLabel (getUnique bid))
- B (TLabel lbl) -> text "\tb" <+> ppr lbl
- B (TReg r) -> text "\tbr" <+> pprReg W64 r
+ B (TBlock bid) -> text "\tbl" <+> ppr (mkLocalBlockLabel (getUnique bid))
+ B (TLabel lbl) -> text "\tbl" <+> ppr lbl
+ B (TReg r) -> text "\tblr" <+> pprReg W64 r
BL (TBlock bid) -> text "\tbl" <+> ppr (mkLocalBlockLabel (getUnique bid))
BL (TLabel lbl) -> text "\tbl" <+> ppr lbl
@@ -483,22 +483,22 @@ pprInstr platform instr = case instr of
text "\tstrh" <+> pprOp o1 <> comma <+> pprOp o2
STR f o1 o2 -> text "\tstr" <+> pprOp o1 <> comma <+> pprOp o2
- -- LDR f o1 (OpImm (ImmIndex lbl off)) ->
- -- text "\tadrp" <+> pprOp o1 <> comma <+> ppr lbl $$
- -- text "\tadd" <+> pprOp o1 <> comma <+> pprOp o1 <> comma <+> text ":lo12:" <> ppr lbl $$
- -- text "\tadd" <+> pprOp o1 <> comma <+> pprOp o1 <> comma <+> char '#' <> int off -- XXX: check that off is in 12bits.
- -- always GOT loads
LDR f o1 (OpImm (ImmIndex lbl off)) ->
- text "\tadrp" <+> pprOp o1 <> comma <+> text ":got:" <> ppr lbl $$
- text "\tldr" <+> pprOp o1 <> comma <+> text "[" <> pprOp o1 <> comma <+> text":got_lo12:" <> ppr lbl <> text "]" $$
+ text "\tadrp" <+> pprOp o1 <> comma <+> ppr lbl $$
+ text "\tadd" <+> pprOp o1 <> comma <+> pprOp o1 <> comma <+> text ":lo12:" <> ppr lbl $$
text "\tadd" <+> pprOp o1 <> comma <+> pprOp o1 <> comma <+> char '#' <> int off -- XXX: check that off is in 12bits.
+ -- always GOT loads
+ -- LDR f o1 (OpImm (ImmIndex lbl off)) ->
+ -- text "\tadrp" <+> pprOp o1 <> comma <+> text ":got:" <> ppr lbl $$
+ -- text "\tldr" <+> pprOp o1 <> comma <+> text "[" <> pprOp o1 <> comma <+> text":got_lo12:" <> ppr lbl <> text "]" $$
+ -- text "\tadd" <+> pprOp o1 <> comma <+> pprOp o1 <> comma <+> char '#' <> int off -- XXX: check that off is in 12bits.
- -- LDR f o1 (OpImm (ImmCLbl lbl)) ->
- -- text "\tadrp" <+> pprOp o1 <> comma <+> ppr lbl $$
- -- text "\tadd" <+> pprOp o1 <> comma <+> pprOp o1 <> comma <+> text ":lo12:" <> ppr lbl
LDR f o1 (OpImm (ImmCLbl lbl)) ->
- text "\tadrp" <+> pprOp o1 <> comma <+> text ":got:" <> ppr lbl $$
- text "\tldr" <+> pprOp o1 <> comma <+> text "[" <> pprOp o1 <> comma <+> text":got_lo12:" <> ppr lbl <> text "]"
+ text "\tadrp" <+> pprOp o1 <> comma <+> ppr lbl $$
+ text "\tadd" <+> pprOp o1 <> comma <+> pprOp o1 <> comma <+> text ":lo12:" <> ppr lbl
+ -- LDR f o1 (OpImm (ImmCLbl lbl)) ->
+ -- text "\tadrp" <+> pprOp o1 <> comma <+> text ":got:" <> ppr lbl $$
+ -- text "\tldr" <+> pprOp o1 <> comma <+> text "[" <> pprOp o1 <> comma <+> text":got_lo12:" <> ppr lbl <> text "]"
LDR f o1@(OpReg W8 (RegReal (RealRegSingle i))) o2 | i < 32 ->
text "\tldrsb" <+> pprOp o1 <> comma <+> pprOp o2
=====================================
compiler/GHC/CmmToAsm/Instr.hs
=====================================
@@ -141,7 +141,7 @@ class Instruction instr where
-> Reg -- ^ the reg to spill
-> Int -- ^ the current stack delta
-> Int -- ^ spill slot to use
- -> (Int, [instr]) -- ^ (new stack delta, instruction)
+ -> instr -- ^ instructions
-- | An instruction to reload a register from a spill slot.
@@ -150,7 +150,7 @@ class Instruction instr where
-> Reg -- ^ the reg to reload.
-> Int -- ^ the current stack delta
-> Int -- ^ the spill slot to use
- -> (Int, [instr]) -- ^ (new stack delta, instruction)
+ -> instr -- ^ instructions
-- | See if this instruction is telling us the current C stack delta
takeDeltaInstr
=====================================
compiler/GHC/CmmToAsm/PPC/Instr.hs
=====================================
@@ -541,7 +541,7 @@ ppc_mkSpillInstr
-> Reg -- register to spill
-> Int -- current stack delta
-> Int -- spill slot to use
- -> (Int, [Instr])
+ -> Instr
ppc_mkSpillInstr config reg delta slot
= let platform = ncgPlatform config
@@ -558,7 +558,7 @@ ppc_mkSpillInstr config reg delta slot
Just _ -> ST
Nothing -> STFAR -- pseudo instruction: 32 bit offsets
- in (delta, [instr fmt reg (AddrRegImm sp (ImmInt (off-delta)))])
+ in instr fmt reg (AddrRegImm sp (ImmInt (off-delta)))
ppc_mkLoadInstr
@@ -566,7 +566,7 @@ ppc_mkLoadInstr
-> Reg -- register to load
-> Int -- current stack delta
-> Int -- spill slot to use
- -> (Int, [Instr])
+ -> Instr
ppc_mkLoadInstr config reg delta slot
= let platform = ncgPlatform config
@@ -583,7 +583,7 @@ ppc_mkLoadInstr config reg delta slot
Just _ -> LD
Nothing -> LDFAR -- pseudo instruction: 32 bit offsets
- in (delta, [instr fmt reg (AddrRegImm sp (ImmInt (off-delta)))])
+ in instr fmt reg (AddrRegImm sp (ImmInt (off-delta)))
-- | The size of a minimal stackframe header including minimal
=====================================
compiler/GHC/CmmToAsm/Reg/Linear.hs
=====================================
@@ -701,7 +701,7 @@ saveClobberedTemps clobbered dying
let new_assign = addToUFM assig temp (InBoth reg slot)
- clobber new_assign (spill ++ instrs) rest
+ clobber new_assign (spill : instrs) rest
@@ -922,7 +922,7 @@ allocRegsAndSpill_spill reading keep spills alloc r rs assig spill_loc
(spill_insn, slot) <- spillR (RegReal my_reg) temp_to_push_out
let spill_store = (if reading then id else reverse)
-- COMMENT (fsLit "spill alloc"):
- spill_insn
+ [spill_insn]
-- record that this temp was spilled
recordSpill (SpillAlloc temp_to_push_out)
@@ -972,7 +972,7 @@ loadTemp vreg (ReadMem slot) hreg spills
= do
insn <- loadR (RegReal hreg) slot
recordSpill (SpillLoad $ getUnique vreg)
- return $ {- COMMENT (fsLit "spill load") : -} insn ++ spills
+ return $ {- COMMENT (fsLit "spill load") : -} insn : spills
loadTemp _ _ _ spills =
return spills
=====================================
compiler/GHC/CmmToAsm/Reg/Linear/JoinToTargets.hs
=====================================
@@ -28,8 +28,6 @@ import GHC.Types.Unique
import GHC.Types.Unique.FM
import GHC.Types.Unique.Set
-import GHC.Utils.Monad (concatMapM)
-
-- | For a jump instruction at the end of a block, generate fixup code so its
-- vregs are in the correct regs for its destination.
--
@@ -306,7 +304,7 @@ handleComponent
-- go via a spill slot.
--
handleComponent delta _ (AcyclicSCC (DigraphNode vreg src dsts))
- = concatMapM (makeMove delta vreg src) dsts
+ = mapM (makeMove delta vreg src) dsts
-- Handle some cyclic moves.
@@ -340,7 +338,7 @@ handleComponent delta instr
-- make sure to do all the reloads after all the spills,
-- so we don't end up clobbering the source values.
- return (instrSpill ++ concat remainingFixUps ++ instrLoad)
+ return ([instrSpill] ++ concat remainingFixUps ++ [instrLoad])
handleComponent _ _ (CyclicSCC _)
= panic "Register Allocator: handleComponent cyclic"
@@ -354,28 +352,22 @@ makeMove
-> Unique -- ^ unique of the vreg that we're moving.
-> Loc -- ^ source location.
-> Loc -- ^ destination location.
- -> RegM freeRegs [instr] -- ^ move instruction.
+ -> RegM freeRegs instr -- ^ move instruction.
-makeMove _ vreg src dst
+makeMove delta vreg src dst
= do config <- getConfig
let platform = ncgPlatform config
case (src, dst) of
(InReg s, InReg d) ->
do recordSpill (SpillJoinRR vreg)
- return $ [mkRegRegMoveInstr platform (RegReal s) (RegReal d)]
+ return $ mkRegRegMoveInstr platform (RegReal s) (RegReal d)
(InMem s, InReg d) ->
do recordSpill (SpillJoinRM vreg)
- delta <- getDeltaR
- let (new_delta, instrs) = mkLoadInstr config (RegReal d) delta s
- setDeltaR new_delta
- return instrs
+ return $ mkLoadInstr config (RegReal d) delta s
(InReg s, InMem d) ->
do recordSpill (SpillJoinRM vreg)
- delta <- getDeltaR
- let (new_delta, instrs) = mkSpillInstr config (RegReal s) delta d
- setDeltaR new_delta
- return instrs
+ return $ mkSpillInstr config (RegReal s) delta d
_ ->
-- we don't handle memory to memory moves.
-- they shouldn't happen because we don't share
=====================================
compiler/GHC/CmmToAsm/Reg/Linear/State.hs
=====================================
@@ -127,22 +127,20 @@ makeRAStats state
spillR :: Instruction instr
- => Reg -> Unique -> RegM freeRegs ([instr], Int)
+ => Reg -> Unique -> RegM freeRegs (instr, Int)
spillR reg temp = RegM $ \s ->
let (stack1,slot) = getStackSlotFor (ra_stack s) temp
- (new_delta, instrs) = mkSpillInstr (ra_config s) reg (ra_delta s) slot
+ instr = mkSpillInstr (ra_config s) reg (ra_delta s) slot
in
- RA_Result s{ra_stack=stack1, ra_delta=new_delta} (instrs,slot)
+ RA_Result s{ra_stack=stack1} (instr,slot)
loadR :: Instruction instr
- => Reg -> Int -> RegM freeRegs [instr]
+ => Reg -> Int -> RegM freeRegs instr
loadR reg slot = RegM $ \s ->
- let (new_delta, instrs) = mkLoadInstr (ra_config s) reg (ra_delta s) slot
- in
- RA_Result s{ra_delta=new_delta} instrs
+ RA_Result s (mkLoadInstr (ra_config s) reg (ra_delta s) slot)
getFreeRegsR :: RegM freeRegs freeRegs
getFreeRegsR = RegM $ \ s at RA_State{ra_freeregs = freeregs} ->
=====================================
compiler/GHC/CmmToAsm/Reg/Liveness.hs
=====================================
@@ -529,15 +529,11 @@ stripLiveBlock config (BasicBlock i lis)
spillNat acc (LiveInstr (SPILL reg slot) _ : instrs)
= do delta <- get
- let (new_delta, instrs') = mkSpillInstr config reg delta slot
- put new_delta
- spillNat (instrs' ++ acc) instrs
+ spillNat (mkSpillInstr config reg delta slot : acc) instrs
spillNat acc (LiveInstr (RELOAD slot reg) _ : instrs)
= do delta <- get
- let (new_delta, instrs') = mkLoadInstr config reg delta slot
- put new_delta
- spillNat (instrs' ++ acc) instrs
+ spillNat (mkLoadInstr config reg delta slot : acc) instrs
spillNat acc (LiveInstr (Instr instr) _ : instrs)
| Just i <- takeDeltaInstr instr
=====================================
compiler/GHC/CmmToAsm/SPARC/Instr.hs
=====================================
@@ -373,7 +373,7 @@ sparc_mkSpillInstr
-> Reg -- ^ register to spill
-> Int -- ^ current stack delta
-> Int -- ^ spill slot to use
- -> (Int, [Instr])
+ -> Instr
sparc_mkSpillInstr config reg delta slot
= let platform = ncgPlatform config
@@ -384,7 +384,7 @@ sparc_mkSpillInstr config reg delta slot
RcFloat -> FF32
RcDouble -> FF64
- in (delta, [ST fmt reg (fpRel (negate off_w))])
+ in ST fmt reg (fpRel (negate off_w))
-- | Make a spill reload instruction.
@@ -393,7 +393,7 @@ sparc_mkLoadInstr
-> Reg -- ^ register to load into
-> Int -- ^ current stack delta
-> Int -- ^ spill slot to use
- -> (Int, [Instr])
+ -> Instr
sparc_mkLoadInstr config reg delta slot
= let platform = ncgPlatform config
@@ -404,7 +404,7 @@ sparc_mkLoadInstr config reg delta slot
RcFloat -> FF32
RcDouble -> FF64
- in (delta, [LD fmt (fpRel (- off_w)) reg])
+ in LD fmt (fpRel (- off_w)) reg
--------------------------------------------------------------------------------
=====================================
compiler/GHC/CmmToAsm/X86/Instr.hs
=====================================
@@ -668,15 +668,15 @@ x86_mkSpillInstr
-> Reg -- register to spill
-> Int -- current stack delta
-> Int -- spill slot to use
- -> (Int, [Instr])
+ -> Instr
x86_mkSpillInstr config reg delta slot
= let off = spillSlotToOffset platform slot - delta
in
case targetClassOfReg platform reg of
- RcInteger -> (delta, [MOV (archWordFormat is32Bit)
- (OpReg reg) (OpAddr (spRel platform off))])
- RcDouble -> (delta, [MOV FF64 (OpReg reg) (OpAddr (spRel platform off))])
+ RcInteger -> MOV (archWordFormat is32Bit)
+ (OpReg reg) (OpAddr (spRel platform off))
+ RcDouble -> MOV FF64 (OpReg reg) (OpAddr (spRel platform off))
_ -> panic "X86.mkSpillInstr: no match"
where platform = ncgPlatform config
is32Bit = target32Bit platform
@@ -687,15 +687,15 @@ x86_mkLoadInstr
-> Reg -- register to load
-> Int -- current stack delta
-> Int -- spill slot to use
- -> (Int, [Instr])
+ -> Instr
x86_mkLoadInstr config reg delta slot
= let off = spillSlotToOffset platform slot - delta
in
case targetClassOfReg platform reg of
- RcInteger -> (delta, [MOV (archWordFormat is32Bit)
- (OpAddr (spRel platform off)) (OpReg reg)])
- RcDouble -> (delta, [MOV FF64 (OpAddr (spRel platform off)) (OpReg reg)])
+ RcInteger -> MOV (archWordFormat is32Bit)
+ (OpAddr (spRel platform off)) (OpReg reg)
+ RcDouble -> MOV FF64 (OpAddr (spRel platform off)) (OpReg reg)
_ -> panic "X86.x86_mkLoadInstr"
where platform = ncgPlatform config
is32Bit = target32Bit platform
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/commit/cf52b0a164ea3a0406d6aa4e581a24818da03786
--
View it on GitLab: https://gitlab.haskell.org/ghc/ghc/-/commit/cf52b0a164ea3a0406d6aa4e581a24818da03786
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