[commit: ghc] master: llvm-targets: drop soft-float (60b0645)

[git at git.haskell.org]

Repository : ssh://git@git.haskell.org/ghc

On branch  : master
Link       : http://ghc.haskell.org/trac/ghc/changeset/60b06456ddef08bd8a8a47497a6cbefbb5e359fb/ghc

>---------------------------------------------------------------

commit 60b06456ddef08bd8a8a47497a6cbefbb5e359fb
Author: Moritz Angermann <moritz.angermann at gmail.com>
Date:   Mon Sep 25 14:17:11 2017 +0800

    llvm-targets: drop soft-float
    
    Summary:
    The llvm-targets file records `mattr` values, and
    while interrogating `clang` for the target, we might
    stumble upon `+soft-float-abi`, however ghc does not support
    full soft-float, and as such passing `+soft-float` to `llc`
    will result in segfaults for any function passing float
    registers F1, ... in the ARM Instruction Selection Pass.
    
    Reviewers: bgamari, austin
    
    Reviewed By: bgamari
    
    Subscribers: rwbarton, thomie
    
    Differential Revision: https://phabricator.haskell.org/D4030


>---------------------------------------------------------------

60b06456ddef08bd8a8a47497a6cbefbb5e359fb
 llvm-targets                          |  8 ++++----
 utils/llvm-targets/gen-data-layout.sh | 15 ++++++++++++++-
 2 files changed, 18 insertions(+), 5 deletions(-)

diff --git a/llvm-targets b/llvm-targets
index 2ac0f87..3c9da1e 100644
--- a/llvm-targets
+++ b/llvm-targets
@@ -6,17 +6,17 @@
 ,("armv7-unknown-linux-gnueabihf", ("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64", "generic", ""))
 ,("aarch64-unknown-linux-gnu", ("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128", "generic", "+neon"))
 ,("aarch64-unknown-linux", ("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128", "generic", "+neon"))
-,("armv7a-unknown-linux-gnueabi", ("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64", "generic", "+soft-float-abi"))
+,("armv7a-unknown-linux-gnueabi", ("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64", "generic", ""))
 ,("i386-unknown-linux-gnu", ("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128", "pentium4", ""))
 ,("i386-unknown-linux", ("e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128", "pentium4", ""))
 ,("x86_64-unknown-linux-gnu", ("e-m:e-i64:64-f80:128-n8:16:32:64-S128", "x86-64", ""))
 ,("x86_64-unknown-linux", ("e-m:e-i64:64-f80:128-n8:16:32:64-S128", "x86-64", ""))
-,("armv7-unknown-linux-androideabi", ("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64", "generic", "+soft-float-abi"))
+,("armv7-unknown-linux-androideabi", ("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64", "generic", ""))
 ,("aarch64-unknown-linux-android", ("e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128", "generic", "+neon"))
-,("arm-unknown-nto-qnx-eabi", ("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64", "arm7tdmi", "+soft-float-abi +strict-align"))
+,("arm-unknown-nto-qnx-eabi", ("e-m:e-p:32:32-i64:64-v128:64:128-a:0:32-n32-S64", "arm7tdmi", "+strict-align"))
 ,("i386-apple-darwin", ("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128", "yonah", ""))
 ,("x86_64-apple-darwin", ("e-m:o-i64:64-f80:128-n8:16:32:64-S128", "core2", ""))
-,("armv7-apple-ios", ("e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32", "generic", "+soft-float-abi"))
+,("armv7-apple-ios", ("e-m:o-p:32:32-f64:32:64-v64:32:64-v128:32:128-a:0:32-n32-S32", "generic", ""))
 ,("aarch64-apple-ios", ("e-m:o-i64:64-i128:128-n32:64-S128", "generic", "+neon"))
 ,("i386-apple-ios", ("e-m:o-p:32:32-f64:32:64-f80:128-n8:16:32-S128", "yonah", ""))
 ,("x86_64-apple-ios", ("e-m:o-i64:64-f80:128-n8:16:32:64-S128", "core2", ""))
diff --git a/utils/llvm-targets/gen-data-layout.sh b/utils/llvm-targets/gen-data-layout.sh
index 79068e9..95c629c 100755
--- a/utils/llvm-targets/gen-data-layout.sh
+++ b/utils/llvm-targets/gen-data-layout.sh
@@ -36,7 +36,20 @@ function get_cpu_and_attr() {
     while [ "$#" -gt 0 ]; do
         case "$1" in
             -target-cpu) CPU=$2; shift 2;;
-            -target-feature) ATTR+=("$2"); shift 2;;
+            -target-feature)
+                # translate clang to opt/llc target features
+                case "$2" in
+                    # we don't have support in GHC for proper soft-float.
+                    # if we extend the `llvm-target` file to contain two
+                    # additional columns for opt and llc flags, we could
+                    # pass -float-abi=soft; However ghc will use float
+                    # registers unconditionally on arm, and as such true
+                    # soft float with the registered llvm backed will is
+                    # currently not possible.
+                    +soft-float-abi) shift 2;;
+                    *) ATTR+=("$2"); shift 2;;
+                esac
+                ;;
             *) shift 1;;
         esac
     done