[commit: ghc] wip/angerman/llvmng: No SMP for Pre Armv7 (bd4dafb)
git at git.haskell.org
git at git.haskell.org
Fri Nov 24 06:52:44 UTC 2017
Repository : ssh://git@git.haskell.org/ghc
On branch : wip/angerman/llvmng
Link : http://ghc.haskell.org/trac/ghc/changeset/bd4dafb9b90c637bbf7921fcd5cd525dba243c1e/ghc
>---------------------------------------------------------------
commit bd4dafb9b90c637bbf7921fcd5cd525dba243c1e
Author: Moritz Angermann <moritz.angermann at gmail.com>
Date: Fri Nov 24 13:00:16 2017 +0800
No SMP for Pre Armv7
So why don't we use NOSMP and the make system logic? Because it's convoluted and
we'd need to replicate the convoluted logic in Hadrian as well. As such we
also do not need the ARM_ISA logic in the make based build system anymore.
>---------------------------------------------------------------
bd4dafb9b90c637bbf7921fcd5cd525dba243c1e
aclocal.m4 | 1 -
includes/stg/Regs.h | 4 ++--
includes/stg/SMP.h | 6 +++---
mk/config.mk.in | 5 -----
mk/project.mk.in | 3 ---
rts/RtsFlags.c | 8 ++++----
rts/Schedule.c | 2 +-
7 files changed, 10 insertions(+), 19 deletions(-)
diff --git a/aclocal.m4 b/aclocal.m4
index c77c8de..b67891f 100644
--- a/aclocal.m4
+++ b/aclocal.m4
@@ -455,7 +455,6 @@ AC_DEFUN([GET_ARM_ISA],
)]
)
- AC_SUBST(ARM_ISA)
])
diff --git a/includes/stg/Regs.h b/includes/stg/Regs.h
index cf9e306..1f19ce1 100644
--- a/includes/stg/Regs.h
+++ b/includes/stg/Regs.h
@@ -422,7 +422,7 @@ struct PartCapability_ {
/* No such thing as a MainCapability under THREADED_RTS - each thread must have
* its own Capability.
*/
-#if IN_STG_CODE && !(defined(THREADED_RTS) && !defined(NOSMP))
+#if IN_STG_CODE && !(defined(THREADED_RTS) && !defined(NOSMP) && !defined(arm_HOST_ARCH_PRE_ARMv7))
extern W_ MainCapability[];
#endif
@@ -438,7 +438,7 @@ extern W_ MainCapability[];
GLOBAL_REG_DECL(StgRegTable *,BaseReg,REG_Base)
#define ASSIGN_BaseReg(e) (BaseReg = (e))
#else
-#if defined(THREADED_RTS) && !defined(NOSMP)
+#if defined(THREADED_RTS) && !defined(NOSMP) && !defined(arm_HOST_ARCH_PRE_ARMv7)
#error BaseReg must be in a register for THREADED_RTS
#endif
#define BaseReg (&((struct PartCapability_ *)MainCapability)->r)
diff --git a/includes/stg/SMP.h b/includes/stg/SMP.h
index 4020aef..1e24f90 100644
--- a/includes/stg/SMP.h
+++ b/includes/stg/SMP.h
@@ -184,7 +184,7 @@ busy_wait_nop(void)
*/
EXTERN_INLINE void
write_barrier(void) {
-#if defined(NOSMP)
+#if defined(NOSMP) || defined(arm_HOST_ARCH_PRE_ARMv7)
return;
#elif defined(i386_HOST_ARCH) || defined(x86_64_HOST_ARCH)
__asm__ __volatile__ ("" : : : "memory");
@@ -203,7 +203,7 @@ write_barrier(void) {
EXTERN_INLINE void
store_load_barrier(void) {
-#if defined(NOSMP)
+#if defined(NOSMP) || defined(arm_HOST_ARCH_PRE_ARMv7)
return;
#elif defined(i386_HOST_ARCH)
__asm__ __volatile__ ("lock; addl $0,0(%%esp)" : : : "memory");
@@ -225,7 +225,7 @@ store_load_barrier(void) {
EXTERN_INLINE void
load_load_barrier(void) {
-#if defined(NOSMP)
+#if defined(NOSMP) || defined(arm_HOST_ARCH_PRE_ARMv7)
return;
#elif defined(i386_HOST_ARCH)
__asm__ __volatile__ ("" : : : "memory");
diff --git a/mk/config.mk.in b/mk/config.mk.in
index b046abe..ac7222a 100644
--- a/mk/config.mk.in
+++ b/mk/config.mk.in
@@ -185,12 +185,7 @@ GhcWithNativeCodeGen := $(strip\
# ArchSupportsSMP should be set iff there is support for that arch in
# includes/stg/SMP.h
-ifeq "$(TargetArch_CPP)" "arm"
-# We don't support load/store barriers pre-ARMv7. See #10433.
-ArchSupportsSMP=$(if $(filter $(ARM_ISA),ARMv5 ARMv6),NO,YES)
-else
ArchSupportsSMP=$(strip $(patsubst $(TargetArch_CPP), YES, $(findstring $(TargetArch_CPP), i386 x86_64 sparc powerpc powerpc64 powerpc64le aarch64)))
-endif
# The THREADED_RTS requires `BaseReg` to be in a register and the
# `GhcUnregisterised` mode doesn't allow that.
diff --git a/mk/project.mk.in b/mk/project.mk.in
index d620ed5..feba5d0 100644
--- a/mk/project.mk.in
+++ b/mk/project.mk.in
@@ -160,6 +160,3 @@ CC_CLANG_BACKEND = @CC_CLANG_BACKEND@
# Is the stage0 compiler affected by Bug #9439?
GHC_LLVM_AFFECTED_BY_9439 = @GHC_LLVM_AFFECTED_BY_9439@
-ifeq "$(TargetArch_CPP)" "arm"
-ARM_ISA=@ARM_ISA@
-endif
diff --git a/rts/RtsFlags.c b/rts/RtsFlags.c
index ecb9228..b791fb9 100644
--- a/rts/RtsFlags.c
+++ b/rts/RtsFlags.c
@@ -406,7 +406,7 @@ usage_text[] = {
" binary event log file instead.",
"",
#endif /* DEBUG */
-#if defined(THREADED_RTS) && !defined(NOSMP)
+#if defined(THREADED_RTS) && !defined(NOSMP) && !defined(arm_HOST_ARCH_PRE_ARMv7)
" -N[<n>] Use <n> processors (default: 1, -N alone determines",
" the number of processors to use automatically)",
" -maxN[<n>] Use up to <n> processors automatically",
@@ -1062,7 +1062,7 @@ error = true;
case 'm':
/* Case for maxN feature request ticket #10728, it's a little
odd being so far from the N case. */
-#if !defined(NOSMP)
+#if !defined(NOSMP) && !defined(arm_HOST_ARCH_PRE_ARMv7)
if (strncmp("maxN", &rts_argv[arg][1], 4) == 0) {
OPTION_SAFE;
THREADED_BUILD_ONLY(
@@ -1096,7 +1096,7 @@ error = true;
RtsFlags.GcFlags.pcFreeHeap > 100)
bad_option( rts_argv[arg] );
break;
-#if !defined(NOSMP)
+#if !defined(NOSMP) && !defined(arm_HOST_ARCH_PRE_ARMv7)
}
#endif
case 'G':
@@ -1284,7 +1284,7 @@ error = true;
}
break;
-#if !defined(NOSMP)
+#if !defined(NOSMP) && !defined(arm_HOST_ARCH_PRE_ARMv7)
case 'N':
OPTION_SAFE;
THREADED_BUILD_ONLY(
diff --git a/rts/Schedule.c b/rts/Schedule.c
index 8002ac3..4773ed5 100644
--- a/rts/Schedule.c
+++ b/rts/Schedule.c
@@ -2153,7 +2153,7 @@ setNumCapabilities (uint32_t new_n_capabilities USED_IF_THREADS)
errorBelch("setNumCapabilities: not supported in the non-threaded RTS");
}
return;
-#elif defined(NOSMP)
+#elif defined(NOSMP) || defined(arm_HOST_ARCH_PRE_ARMv7)
if (new_n_capabilities != 1) {
errorBelch("setNumCapabilities: not supported on this platform");
}
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